diff options
Diffstat (limited to 'drivers/gpu/drm/arm')
| -rw-r--r-- | drivers/gpu/drm/arm/hdlcd_crtc.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/arm/hdlcd_drv.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/arm/malidp_crtc.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/arm/malidp_drv.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/arm/malidp_drv.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/arm/malidp_hw.c | 19 | ||||
| -rw-r--r-- | drivers/gpu/drm/arm/malidp_planes.c | 30 |
7 files changed, 45 insertions, 37 deletions
diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index 1a3359c0f6cd..d67b6f15e8b8 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -261,21 +261,14 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane, { struct drm_framebuffer *fb = plane->state->fb; struct hdlcd_drm_private *hdlcd; - struct drm_gem_cma_object *gem; - u32 src_x, src_y, dest_h; + u32 dest_h; dma_addr_t scanout_start; if (!fb) return; - src_x = plane->state->src.x1 >> 16; - src_y = plane->state->src.y1 >> 16; dest_h = drm_rect_height(&plane->state->dst); - gem = drm_fb_cma_get_gem_obj(fb, 0); - - scanout_start = gem->paddr + fb->offsets[0] + - src_y * fb->pitches[0] + - src_x * fb->format->cpp[0]; + scanout_start = drm_fb_cma_get_gem_addr(fb, plane->state, 0); hdlcd = plane->dev->dev_private; hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]); diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c index 0f49c4b12772..d3da87fbd85a 100644 --- a/drivers/gpu/drm/arm/hdlcd_drv.c +++ b/drivers/gpu/drm/arm/hdlcd_drv.c @@ -297,6 +297,9 @@ static int hdlcd_drm_bind(struct device *dev) if (ret) goto err_free; + /* Set the CRTC's port so that the encoder component can find it */ + hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); + ret = component_bind_all(dev, drm); if (ret) { DRM_ERROR("Failed to bind all components\n"); @@ -346,6 +349,8 @@ err_vblank: err_pm_active: component_unbind_all(dev, drm); err_unload: + of_node_put(hdlcd->crtc.port); + hdlcd->crtc.port = NULL; drm_irq_uninstall(drm); of_reserved_mem_device_release(drm->dev); err_free: @@ -368,6 +373,8 @@ static void hdlcd_drm_unbind(struct device *dev) } drm_kms_helper_poll_fini(drm); component_unbind_all(dev, drm); + of_node_put(hdlcd->crtc.port); + hdlcd->crtc.port = NULL; drm_vblank_cleanup(drm); pm_runtime_get_sync(drm->dev); drm_irq_uninstall(drm); diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c index 9446a673d469..4bb38a21efec 100644 --- a/drivers/gpu/drm/arm/malidp_crtc.c +++ b/drivers/gpu/drm/arm/malidp_crtc.c @@ -22,9 +22,8 @@ #include "malidp_drv.h" #include "malidp_hw.h" -static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) +static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) { struct malidp_drm *malidp = crtc_to_malidp_device(crtc); struct malidp_hw_device *hwdev = malidp->dev; @@ -40,11 +39,11 @@ static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc, if (rate != req_rate) { DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n", req_rate); - return false; + return MODE_NOCLOCK; } } - return true; + return MODE_OK; } static void malidp_crtc_enable(struct drm_crtc *crtc) @@ -408,7 +407,7 @@ static int malidp_crtc_atomic_check(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = { - .mode_fixup = malidp_crtc_mode_fixup, + .mode_valid = malidp_crtc_mode_valid, .enable = malidp_crtc_enable, .disable = malidp_crtc_disable, .atomic_check = malidp_crtc_atomic_check, diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 0d3eb537d08b..01b13d219917 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -652,7 +652,6 @@ register_fail: drm_kms_helper_poll_fini(drm); fbdev_fail: pm_runtime_get_sync(dev); - drm_vblank_cleanup(drm); vblank_fail: malidp_se_irq_fini(drm); malidp_de_irq_fini(drm); @@ -692,7 +691,6 @@ static void malidp_unbind(struct device *dev) } drm_kms_helper_poll_fini(drm); pm_runtime_get_sync(dev); - drm_vblank_cleanup(drm); malidp_se_irq_fini(drm); malidp_de_irq_fini(drm); component_unbind_all(dev, drm); diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h index 040311ffcaec..2e2033140efc 100644 --- a/drivers/gpu/drm/arm/malidp_drv.h +++ b/drivers/gpu/drm/arm/malidp_drv.h @@ -65,6 +65,6 @@ void malidp_de_planes_destroy(struct drm_device *drm); int malidp_crtc_init(struct drm_device *drm); /* often used combination of rotational bits */ -#define MALIDP_ROTATED_MASK (DRM_ROTATE_90 | DRM_ROTATE_270) +#define MALIDP_ROTATED_MASK (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270) #endif /* __MALIDP_DRV_H__ */ diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 28360b8542f7..17bca99e8ac8 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -766,12 +766,17 @@ static irqreturn_t malidp_de_irq(int irq, void *arg) u32 status, mask, dc_status; irqreturn_t ret = IRQ_NONE; - if (!drm->dev_private) - return IRQ_HANDLED; - hwdev = malidp->dev; de = &hwdev->map.de_irq_map; + /* + * if we are suspended it is likely that we were invoked because + * we share an interrupt line with some other driver, don't try + * to read the hardware registers + */ + if (hwdev->pm_suspended) + return IRQ_NONE; + /* first handle the config valid IRQ */ dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS); if (dc_status & hwdev->map.dc_irq_map.vsync_irq) { @@ -854,6 +859,14 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) struct malidp_hw_device *hwdev = malidp->dev; u32 status, mask; + /* + * if we are suspended it is likely that we were invoked because + * we share an interrupt line with some other driver, don't try + * to read the hardware registers + */ + if (hwdev->pm_suspended) + return IRQ_NONE; + status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS); if (!(status & hwdev->map.se_irq_map.irq_mask)) return IRQ_NONE; diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index 814fda23cead..600fa7bd7f52 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -80,7 +80,7 @@ static void malidp_plane_reset(struct drm_plane *plane) state = kzalloc(sizeof(*state), GFP_KERNEL); if (state) { state->base.plane = plane; - state->base.rotation = DRM_ROTATE_0; + state->base.rotation = DRM_MODE_ROTATE_0; plane->state = &state->base; } } @@ -221,7 +221,7 @@ static int malidp_de_plane_check(struct drm_plane *plane, return ret; /* packed RGB888 / BGR888 can't be rotated or flipped */ - if (state->rotation != DRM_ROTATE_0 && + if (state->rotation != DRM_MODE_ROTATE_0 && (fb->format->format == DRM_FORMAT_RGB888 || fb->format->format == DRM_FORMAT_BGR888)) return -EINVAL; @@ -264,11 +264,9 @@ static void malidp_de_set_plane_pitches(struct malidp_plane *mp, static void malidp_de_plane_update(struct drm_plane *plane, struct drm_plane_state *old_state) { - struct drm_gem_cma_object *obj; struct malidp_plane *mp; const struct malidp_hw_regmap *map; struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); - u16 ptr; u32 src_w, src_h, dest_w, dest_h, val; int i; @@ -285,12 +283,12 @@ static void malidp_de_plane_update(struct drm_plane *plane, for (i = 0; i < ms->n_planes; i++) { /* calculate the offset for the layer's plane registers */ - ptr = mp->layer->ptr + (i << 4); + u16 ptr = mp->layer->ptr + (i << 4); + dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb, + plane->state, i); - obj = drm_fb_cma_get_gem_obj(plane->state->fb, i); - obj->paddr += plane->state->fb->offsets[i]; - malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr); - malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4); + malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr); + malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4); } malidp_de_set_plane_pitches(mp, ms->n_planes, plane->state->fb->pitches); @@ -315,12 +313,12 @@ static void malidp_de_plane_update(struct drm_plane *plane, val &= ~LAYER_ROT_MASK; /* setup the rotation and axis flip bits */ - if (plane->state->rotation & DRM_ROTATE_MASK) - val |= ilog2(plane->state->rotation & DRM_ROTATE_MASK) << + if (plane->state->rotation & DRM_MODE_ROTATE_MASK) + val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << LAYER_ROT_OFFSET; - if (plane->state->rotation & DRM_REFLECT_X) + if (plane->state->rotation & DRM_MODE_REFLECT_X) val |= LAYER_H_FLIP; - if (plane->state->rotation & DRM_REFLECT_Y) + if (plane->state->rotation & DRM_MODE_REFLECT_Y) val |= LAYER_V_FLIP; /* @@ -370,8 +368,8 @@ int malidp_de_planes_init(struct drm_device *drm) struct malidp_plane *plane = NULL; enum drm_plane_type plane_type; unsigned long crtcs = 1 << drm->mode_config.num_crtc; - unsigned long flags = DRM_ROTATE_0 | DRM_ROTATE_90 | DRM_ROTATE_180 | - DRM_ROTATE_270 | DRM_REFLECT_X | DRM_REFLECT_Y; + unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | + DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; u32 *formats; int ret, i, j, n; @@ -420,7 +418,7 @@ int malidp_de_planes_init(struct drm_device *drm) continue; } - drm_plane_create_rotation_property(&plane->base, DRM_ROTATE_0, flags); + drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, plane->layer->base + MALIDP_LAYER_COMPOSE); } |