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path: root/drivers/gpu/drm/amd/display/include
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Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
-rw-r--r--drivers/gpu/drm/amd/display/include/bios_parser_types.h20
1 files changed, 0 insertions, 20 deletions
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index 7de4fa5a0726..0840f69cde99 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -156,13 +156,6 @@ struct bp_transmitter_control {
bool single_pll_mode;
};
-struct bp_blank_crtc_parameters {
- enum controller_id controller_id;
- uint32_t black_color_rcr;
- uint32_t black_color_gy;
- uint32_t black_color_bcb;
-};
-
struct bp_hw_crtc_timing_parameters {
enum controller_id controller_id;
/* horizontal part */
@@ -252,14 +245,6 @@ struct bp_pixel_clock_parameters {
} flags;
};
-struct bp_display_clock_parameters {
- uint32_t target_display_clock; /* KHz */
- /* Actual Display Clock set due to clock divider granularity KHz */
- uint32_t actual_display_clock;
- /* Actual Post Divider ID used to generate the actual clock */
- uint32_t actual_post_divider_id;
-};
-
enum bp_dce_clock_type {
DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
DCECLOCK_TYPE_DPREFCLK = 1
@@ -322,9 +307,4 @@ struct bp_encoder_cap_info {
uint32_t RESERVED:30;
};
-struct bp_gpio_cntl_info {
- uint32_t id;
- enum gpio_pin_output_state state;
-};
-
#endif /*__DAL_BIOS_PARSER_TYPES_H__ */