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path: root/drivers/gpu/drm/amd/display/dc/optc
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/optc')
-rw-r--r--drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
index 2f3bd7648ba7..874cf5d241ad 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
@@ -200,6 +200,7 @@ struct dcn_optc_registers {
uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK;
uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK;
uint32_t OPTC_CLOCK_CONTROL;
+ uint32_t OPTC_WIDTH_CONTROL2;
};
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -590,16 +591,22 @@ struct dcn_optc_registers {
type OTG_V_COUNT_STOP;\
type OTG_V_COUNT_STOP_TIMER;
+#define TG_REG_FIELD_LIST_DCN401(type) \
+ type OPTC_SEGMENT_WIDTH_LAST;
+
+
struct dcn_optc_shift {
TG_REG_FIELD_LIST(uint8_t)
TG_REG_FIELD_LIST_DCN3_2(uint8_t)
TG_REG_FIELD_LIST_DCN3_5(uint8_t)
+ TG_REG_FIELD_LIST_DCN401(uint8_t)
};
struct dcn_optc_mask {
TG_REG_FIELD_LIST(uint32_t)
TG_REG_FIELD_LIST_DCN3_2(uint32_t)
TG_REG_FIELD_LIST_DCN3_5(uint32_t)
+ TG_REG_FIELD_LIST_DCN401(uint32_t)
};
void dcn10_timing_generator_init(struct optc *optc);