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path: root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index cec69cecf521..e9ebbbe256b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -367,6 +367,11 @@ void opp1_program_oppbuf(
*/
REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* Controls the number of padded pixels at the end of a segment */
+ if (REG(OPPBUF_CONTROL1))
+ REG_UPDATE(OPPBUF_CONTROL1, OPPBUF_NUM_SEGMENT_PADDED_PIXELS, oppbuf->num_segment_padded_pixels);
+#endif
}
void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
@@ -393,6 +398,9 @@ static const struct opp_funcs dcn10_opp_funcs = {
.opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
.opp_program_stereo = opp1_program_stereo,
.opp_pipe_clock_control = opp1_pipe_clock_control,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .opp_set_disp_pattern_generator = NULL,
+#endif
.opp_destroy = opp1_destroy
};