diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/sprd/ums512.dtsi | 14 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/sprd/ums9620.dtsi | 14 |
2 files changed, 20 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi index dbdb79f8e959..4c080df48724 100644 --- a/arch/arm64/boot/dts/sprd/ums512.dtsi +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -136,16 +136,22 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; + }; + + pmu-a75 { + compatible = "arm,cortex-a75-pmu"; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CPU6>, <&CPU7>; }; soc: soc { diff --git a/arch/arm64/boot/dts/sprd/ums9620.dtsi b/arch/arm64/boot/dts/sprd/ums9620.dtsi index 2191f0a4811b..2458071320c9 100644 --- a/arch/arm64/boot/dts/sprd/ums9620.dtsi +++ b/arch/arm64/boot/dts/sprd/ums9620.dtsi @@ -144,16 +144,22 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; }; soc: soc { |