summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/tegra30_clocks_data.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-tegra/tegra30_clocks_data.c')
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c1688
1 files changed, 957 insertions, 731 deletions
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index b1243c9e8ef7..c924240cb693 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1,7 +1,7 @@
/*
- * arch/arm/mach-tegra/tegra30_clocks_data.c
+ * arch/arm/mach-tegra/tegra30_clocks.c
*
- * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,6 +18,7 @@
*
*/
+#include <linux/clk-private.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/list.h>
@@ -28,69 +29,165 @@
#include <linux/clk.h>
#include <linux/cpufreq.h>
-#include <asm/clkdev.h>
-
-#include <mach/iomap.h>
-
#include "clock.h"
#include "fuse.h"
#include "tegra30_clocks.h"
-/* Clock definitions */
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
+ _parent_names, _parents, _parent) \
+ static struct clk tegra_##_name = { \
+ .hw = &tegra_##_name##_hw.hw, \
+ .name = #_name, \
+ .rate = _rate, \
+ .ops = _ops, \
+ .flags = _flags, \
+ .parent_names = _parent_names, \
+ .parents = _parents, \
+ .num_parents = ARRAY_SIZE(_parent_names), \
+ .parent = _parent, \
+ };
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+ .hw = {
+ .clk = &tegra_clk_32k,
+ },
+ .fixed_rate = 32768,
+};
static struct clk tegra_clk_32k = {
.name = "clk_32k",
- .rate = 32768,
- .ops = NULL,
- .max_rate = 32768,
+ .hw = &tegra_clk_32k_hw.hw,
+ .ops = &tegra_clk_32k_ops,
+ .flags = CLK_IS_ROOT,
};
-static struct clk tegra_clk_m = {
- .name = "clk_m",
- .flags = ENABLE_ON_INIT,
- .ops = &tegra30_clk_m_ops,
- .reg = 0x1fc,
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+ .hw = {
+ .clk = &tegra_clk_m,
+ },
+ .flags = ENABLE_ON_INIT,
+ .reg = 0x1fc,
.reg_shift = 28,
- .max_rate = 48000000,
+ .max_rate = 48000000,
+};
+static struct clk tegra_clk_m = {
+ .name = "clk_m",
+ .hw = &tegra_clk_m_hw.hw,
+ .ops = &tegra30_clk_m_ops,
+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
};
-static struct clk tegra_clk_m_div2 = {
- .name = "clk_m_div2",
- .ops = &tegra_clk_m_div_ops,
- .parent = &tegra_clk_m,
- .mul = 1,
- .div = 2,
- .state = ON,
- .max_rate = 24000000,
+static const char *clk_m_div_parent_names[] = {
+ "clk_m",
};
-static struct clk tegra_clk_m_div4 = {
- .name = "clk_m_div4",
- .ops = &tegra_clk_m_div_ops,
- .parent = &tegra_clk_m,
- .mul = 1,
- .div = 4,
- .state = ON,
- .max_rate = 12000000,
+static struct clk *clk_m_div_parents[] = {
+ &tegra_clk_m,
};
-static struct clk tegra_pll_ref = {
- .name = "pll_ref",
- .flags = ENABLE_ON_INIT,
- .ops = &tegra_pll_ref_ops,
- .parent = &tegra_clk_m,
- .max_rate = 26000000,
+static struct clk tegra_clk_m_div2;
+static struct clk_tegra tegra_clk_m_div2_hw = {
+ .hw = {
+ .clk = &tegra_clk_m_div2,
+ },
+ .mul = 1,
+ .div = 2,
+ .max_rate = 24000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
+ clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_clk_m_div4;
+static struct clk_tegra tegra_clk_m_div4_hw = {
+ .hw = {
+ .clk = &tegra_clk_m_div4,
+ },
+ .mul = 1,
+ .div = 4,
+ .max_rate = 12000000,
};
+DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
+ clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_pll_ref;
+static struct clk_tegra tegra_pll_ref_hw = {
+ .hw = {
+ .clk = &tegra_pll_ref,
+ },
+ .flags = ENABLE_ON_INIT,
+ .max_rate = 26000000,
+};
+DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
+ clk_m_div_parents, &tegra_clk_m);
+
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
+ _input_max, _cf_min, _cf_max, _vco_min, \
+ _vco_max, _freq_table, _lock_delay, _ops, \
+ _fixed_rate, _clk_cfg_ex, _parent) \
+ static struct clk tegra_##_name; \
+ static const char *_name##_parent_names[] = { \
+ #_parent, \
+ }; \
+ static struct clk *_name##_parents[] = { \
+ &tegra_##_parent, \
+ }; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .flags = _flags, \
+ .reg = _reg, \
+ .max_rate = _max_rate, \
+ .u.pll = { \
+ .input_min = _input_min, \
+ .input_max = _input_max, \
+ .cf_min = _cf_min, \
+ .cf_max = _cf_max, \
+ .vco_min = _vco_min, \
+ .vco_max = _vco_max, \
+ .freq_table = _freq_table, \
+ .lock_delay = _lock_delay, \
+ .fixed_rate = _fixed_rate, \
+ }, \
+ .clk_cfg_ex = _clk_cfg_ex, \
+ }; \
+ DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
+ _name##_parent_names, _name##_parents, \
+ &tegra_##_parent);
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
+ _max_rate, _ops, _parent, _clk_flags) \
+ static const char *_name##_parent_names[] = { \
+ #_parent, \
+ }; \
+ static struct clk *_name##_parents[] = { \
+ &tegra_##_parent, \
+ }; \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .flags = _flags, \
+ .reg = _reg, \
+ .max_rate = _max_rate, \
+ .reg_shift = _reg_shift, \
+ }; \
+ DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
+ _clk_flags, _name##_parent_names, \
+ _name##_parents, &tegra_##_parent);
static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
{ 12000000, 1040000000, 520, 6, 1, 8},
{ 13000000, 1040000000, 480, 6, 1, 8},
- { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
+ { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
{ 19200000, 1040000000, 325, 6, 1, 6},
{ 26000000, 1040000000, 520, 13, 1, 8},
{ 12000000, 832000000, 416, 6, 1, 8},
{ 13000000, 832000000, 832, 13, 1, 8},
- { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
+ { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
{ 19200000, 832000000, 260, 6, 1, 8},
{ 26000000, 832000000, 416, 13, 1, 8},
@@ -108,46 +205,24 @@ static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
{ 12000000, 520000000, 520, 12, 1, 8},
{ 13000000, 520000000, 520, 13, 1, 8},
- { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
+ { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
{ 19200000, 520000000, 325, 12, 1, 6},
{ 26000000, 520000000, 520, 26, 1, 8},
{ 12000000, 416000000, 416, 12, 1, 8},
{ 13000000, 416000000, 416, 13, 1, 8},
- { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
+ { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
{ 19200000, 416000000, 260, 12, 1, 6},
{ 26000000, 416000000, 416, 26, 1, 8},
{ 0, 0, 0, 0, 0, 0 },
};
-static struct clk tegra_pll_c = {
- .name = "pll_c",
- .flags = PLL_HAS_CPCON,
- .ops = &tegra30_pll_ops,
- .reg = 0x80,
- .parent = &tegra_pll_ref,
- .max_rate = 1400000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_c_freq_table,
- .lock_delay = 300,
- },
-};
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
+ 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+ tegra30_pll_ops, 0, NULL, pll_ref);
-static struct clk tegra_pll_c_out1 = {
- .name = "pll_c_out1",
- .ops = &tegra30_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_c,
- .reg = 0x84,
- .reg_shift = 0,
- .max_rate = 700000000,
-};
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
+ tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
{ 12000000, 666000000, 666, 12, 1, 8},
@@ -163,34 +238,12 @@ static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
-static struct clk tegra_pll_m = {
- .name = "pll_m",
- .flags = PLL_HAS_CPCON | PLLM,
- .ops = &tegra30_pll_ops,
- .reg = 0x90,
- .parent = &tegra_pll_ref,
- .max_rate = 800000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1200000000,
- .freq_table = tegra_pll_m_freq_table,
- .lock_delay = 300,
- },
-};
+DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
+ 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
+ 300, tegra30_pll_ops, 0, NULL, pll_ref);
-static struct clk tegra_pll_m_out1 = {
- .name = "pll_m_out1",
- .ops = &tegra30_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_m,
- .reg = 0x94,
- .reg_shift = 0,
- .max_rate = 600000000,
-};
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+ tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
{ 12000000, 216000000, 432, 12, 2, 8},
@@ -201,65 +254,19 @@ static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
-static struct clk tegra_pll_p = {
- .name = "pll_p",
- .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
- .ops = &tegra30_pll_ops,
- .reg = 0xa0,
- .parent = &tegra_pll_ref,
- .max_rate = 432000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_p_freq_table,
- .lock_delay = 300,
- .fixed_rate = 408000000,
- },
-};
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+ 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+ tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
+ pll_ref);
-static struct clk tegra_pll_p_out1 = {
- .name = "pll_p_out1",
- .ops = &tegra30_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa4,
- .reg_shift = 0,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
- .name = "pll_p_out2",
- .ops = &tegra30_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa4,
- .reg_shift = 16,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
- .name = "pll_p_out3",
- .ops = &tegra30_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa8,
- .reg_shift = 0,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
- .name = "pll_p_out4",
- .ops = &tegra30_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa8,
- .reg_shift = 16,
- .max_rate = 432000000,
-};
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+ 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+ 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+ 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+ 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
{ 9600000, 564480000, 294, 5, 1, 4},
@@ -272,34 +279,12 @@ static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
-static struct clk tegra_pll_a = {
- .name = "pll_a",
- .flags = PLL_HAS_CPCON,
- .ops = &tegra30_pll_ops,
- .reg = 0xb0,
- .parent = &tegra_pll_p_out1,
- .max_rate = 700000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_a_freq_table,
- .lock_delay = 300,
- },
-};
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
+ 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
+ 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
-static struct clk tegra_pll_a_out0 = {
- .name = "pll_a_out0",
- .ops = &tegra30_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_a,
- .reg = 0xb4,
- .reg_shift = 0,
- .max_rate = 100000000,
-};
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
+ pll_a, CLK_IGNORE_UNUSED);
static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
{ 12000000, 216000000, 216, 12, 1, 4},
@@ -322,59 +307,20 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
-static struct clk tegra_pll_d = {
- .name = "pll_d",
- .flags = PLL_HAS_CPCON | PLLD,
- .ops = &tegra_plld_ops,
- .reg = 0xd0,
- .parent = &tegra_pll_ref,
- .max_rate = 1000000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 40000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 40000000,
- .vco_max = 1000000000,
- .freq_table = tegra_pll_d_freq_table,
- .lock_delay = 1000,
- },
-};
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+ 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+ 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
-static struct clk tegra_pll_d_out0 = {
- .name = "pll_d_out0",
- .ops = &tegra30_pll_div_ops,
- .flags = DIV_2 | PLLD,
- .parent = &tegra_pll_d,
- .max_rate = 500000000,
-};
-
-static struct clk tegra_pll_d2 = {
- .name = "pll_d2",
- .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
- .ops = &tegra_plld_ops,
- .reg = 0x4b8,
- .parent = &tegra_pll_ref,
- .max_rate = 1000000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 40000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 40000000,
- .vco_max = 1000000000,
- .freq_table = tegra_pll_d_freq_table,
- .lock_delay = 1000,
- },
-};
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+ pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
-static struct clk tegra_pll_d2_out0 = {
- .name = "pll_d2_out0",
- .ops = &tegra30_pll_div_ops,
- .flags = DIV_2 | PLLD,
- .parent = &tegra_pll_d2,
- .max_rate = 500000000,
-};
+DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
+ 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
+ tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
+ pll_ref);
+
+DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+ pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
{ 12000000, 480000000, 960, 12, 2, 12},
@@ -385,24 +331,9 @@ static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
-static struct clk tegra_pll_u = {
- .name = "pll_u",
- .flags = PLL_HAS_CPCON | PLLU,
- .ops = &tegra30_pll_ops,
- .reg = 0xc0,
- .parent = &tegra_pll_ref,
- .max_rate = 480000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 40000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 480000000,
- .vco_max = 960000000,
- .freq_table = tegra_pll_u_freq_table,
- .lock_delay = 1000,
- },
-};
+DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
+ 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
+ 1000, tegra30_pll_ops, 0, NULL, pll_ref);
static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
/* 1.7 GHz */
@@ -464,33 +395,12 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
-static struct clk tegra_pll_x = {
- .name = "pll_x",
- .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
- .ops = &tegra30_pll_ops,
- .reg = 0xe0,
- .parent = &tegra_pll_ref,
- .max_rate = 1700000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1700000000,
- .freq_table = tegra_pll_x_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_x_out0 = {
- .name = "pll_x_out0",
- .ops = &tegra30_pll_div_ops,
- .flags = DIV_2 | PLLX,
- .parent = &tegra_pll_x,
- .max_rate = 850000000,
-};
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
+ 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
+ tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
+DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
+ pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
/* PLLE special case: use cpcon field to store cml divider value */
@@ -499,518 +409,835 @@ static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
-static struct clk tegra_pll_e = {
- .name = "pll_e",
- .flags = PLL_ALT_MISC_REG,
- .ops = &tegra30_plle_ops,
- .reg = 0xe8,
- .max_rate = 100000000,
- .u.pll = {
- .input_min = 12000000,
- .input_max = 216000000,
- .cf_min = 12000000,
- .cf_max = 12000000,
- .vco_min = 1200000000,
- .vco_max = 2400000000U,
- .freq_table = tegra_pll_e_freq_table,
- .lock_delay = 300,
- .fixed_rate = 100000000,
- },
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
+ 12000000, 12000000, 1200000000, 2400000000U,
+ tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
+ pll_ref);
+
+static const char *mux_plle[] = {
+ "pll_e",
+};
+
+static struct clk *mux_plle_p[] = {
+ &tegra_pll_e,
};
-static struct clk tegra_cml0_clk = {
- .name = "cml0",
- .parent = &tegra_pll_e,
- .ops = &tegra_cml_clk_ops,
- .reg = 0x48c,
- .max_rate = 100000000,
- .u.periph = {
+static struct clk tegra_cml0;
+static struct clk_tegra tegra_cml0_hw = {
+ .hw = {
+ .clk = &tegra_cml0,
+ },
+ .reg = 0x48c,
+ .fixed_rate = 100000000,
+ .u.periph = {
.clk_num = 0,
},
};
+DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
+ mux_plle_p, &tegra_pll_e);
-static struct clk tegra_cml1_clk = {
- .name = "cml1",
- .parent = &tegra_pll_e,
- .ops = &tegra_cml_clk_ops,
- .reg = 0x48c,
- .max_rate = 100000000,
- .u.periph = {
- .clk_num = 1,
+static struct clk tegra_cml1;
+static struct clk_tegra tegra_cml1_hw = {
+ .hw = {
+ .clk = &tegra_cml1,
+ },
+ .reg = 0x48c,
+ .fixed_rate = 100000000,
+ .u.periph = {
+ .clk_num = 1,
},
};
+DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
+ mux_plle_p, &tegra_pll_e);
-static struct clk tegra_pciex_clk = {
- .name = "pciex",
- .parent = &tegra_pll_e,
- .ops = &tegra_pciex_clk_ops,
- .max_rate = 100000000,
- .u.periph = {
- .clk_num = 74,
+static struct clk tegra_pciex;
+static struct clk_tegra tegra_pciex_hw = {
+ .hw = {
+ .clk = &tegra_pciex,
+ },
+ .reg = 0x48c,
+ .fixed_rate = 100000000,
+ .reset = tegra30_periph_clk_reset,
+ .u.periph = {
+ .clk_num = 74,
},
};
+DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
+ mux_plle_p, &tegra_pll_e);
-/* Audio sync clocks */
-#define SYNC_SOURCE(_id) \
- { \
- .name = #_id "_sync", \
- .rate = 24000000, \
- .max_rate = 24000000, \
- .ops = &tegra_sync_source_ops \
- }
-static struct clk tegra_sync_source_list[] = {
- SYNC_SOURCE(spdif_in),
- SYNC_SOURCE(i2s0),
- SYNC_SOURCE(i2s1),
- SYNC_SOURCE(i2s2),
- SYNC_SOURCE(i2s3),
- SYNC_SOURCE(i2s4),
- SYNC_SOURCE(vimclk),
-};
-
-static struct clk_mux_sel mux_audio_sync_clk[] = {
- { .input = &tegra_sync_source_list[0], .value = 0},
- { .input = &tegra_sync_source_list[1], .value = 1},
- { .input = &tegra_sync_source_list[2], .value = 2},
- { .input = &tegra_sync_source_list[3], .value = 3},
- { .input = &tegra_sync_source_list[4], .value = 4},
- { .input = &tegra_sync_source_list[5], .value = 5},
- { .input = &tegra_pll_a_out0, .value = 6},
- { .input = &tegra_sync_source_list[6], .value = 7},
- { 0, 0 }
-};
-
-#define AUDIO_SYNC_CLK(_id, _index) \
- { \
- .name = #_id, \
- .inputs = mux_audio_sync_clk, \
- .reg = 0x4A0 + (_index) * 4, \
- .max_rate = 24000000, \
- .ops = &tegra30_audio_sync_clk_ops \
- }
-static struct clk tegra_clk_audio_list[] = {
- AUDIO_SYNC_CLK(audio0, 0),
- AUDIO_SYNC_CLK(audio1, 1),
- AUDIO_SYNC_CLK(audio2, 2),
- AUDIO_SYNC_CLK(audio3, 3),
- AUDIO_SYNC_CLK(audio4, 4),
- AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
-};
-
-#define AUDIO_SYNC_2X_CLK(_id, _index) \
- { \
- .name = #_id "_2x", \
- .flags = PERIPH_NO_RESET, \
- .max_rate = 48000000, \
- .ops = &tegra30_clk_double_ops, \
- .reg = 0x49C, \
+#define SYNC_SOURCE(_name) \
+ static struct clk tegra_##_name##_sync; \
+ static struct clk_tegra tegra_##_name##_sync_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name##_sync, \
+ }, \
+ .max_rate = 24000000, \
+ .fixed_rate = 24000000, \
+ }; \
+ static struct clk tegra_##_name##_sync = { \
+ .name = #_name "_sync", \
+ .hw = &tegra_##_name##_sync_hw.hw, \
+ .ops = &tegra_sync_source_ops, \
+ .flags = CLK_IS_ROOT, \
+ };
+
+SYNC_SOURCE(spdif_in);
+SYNC_SOURCE(i2s0);
+SYNC_SOURCE(i2s1);
+SYNC_SOURCE(i2s2);
+SYNC_SOURCE(i2s3);
+SYNC_SOURCE(i2s4);
+SYNC_SOURCE(vimclk);
+
+static struct clk *tegra_sync_source_list[] = {
+ &tegra_spdif_in_sync,
+ &tegra_i2s0_sync,
+ &tegra_i2s1_sync,
+ &tegra_i2s2_sync,
+ &tegra_i2s3_sync,
+ &tegra_i2s4_sync,
+ &tegra_vimclk_sync,
+};
+
+static const char *mux_audio_sync_clk[] = {
+ "spdif_in_sync",
+ "i2s0_sync",
+ "i2s1_sync",
+ "i2s2_sync",
+ "i2s3_sync",
+ "i2s4_sync",
+ "vimclk_sync",
+};
+
+#define AUDIO_SYNC_CLK(_name, _index) \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .max_rate = 24000000, \
+ .reg = 0x4A0 + (_index) * 4, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &tegra_audio_sync_clk_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent_names = mux_audio_sync_clk, \
+ .parents = tegra_sync_source_list, \
+ .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
+ };
+
+AUDIO_SYNC_CLK(audio0, 0);
+AUDIO_SYNC_CLK(audio1, 1);
+AUDIO_SYNC_CLK(audio2, 2);
+AUDIO_SYNC_CLK(audio3, 3);
+AUDIO_SYNC_CLK(audio4, 4);
+AUDIO_SYNC_CLK(audio5, 5);
+
+static struct clk *tegra_clk_audio_list[] = {
+ &tegra_audio0,
+ &tegra_audio1,
+ &tegra_audio2,
+ &tegra_audio3,
+ &tegra_audio4,
+ &tegra_audio5, /* SPDIF */
+};
+
+#define AUDIO_SYNC_2X_CLK(_name, _index) \
+ static const char *_name##_parent_names[] = { \
+ "tegra_" #_name, \
+ }; \
+ static struct clk *_name##_parents[] = { \
+ &tegra_##_name, \
+ }; \
+ static struct clk tegra_##_name##_2x; \
+ static struct clk_tegra tegra_##_name##_2x_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name##_2x, \
+ }, \
+ .flags = PERIPH_NO_RESET, \
+ .max_rate = 48000000, \
+ .reg = 0x49C, \
.reg_shift = 24 + (_index), \
- .parent = &tegra_clk_audio_list[(_index)], \
.u.periph = { \
.clk_num = 113 + (_index), \
}, \
- }
-static struct clk tegra_clk_audio_2x_list[] = {
- AUDIO_SYNC_2X_CLK(audio0, 0),
- AUDIO_SYNC_2X_CLK(audio1, 1),
- AUDIO_SYNC_2X_CLK(audio2, 2),
- AUDIO_SYNC_2X_CLK(audio3, 3),
- AUDIO_SYNC_2X_CLK(audio4, 4),
- AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
-};
-
-#define MUX_I2S_SPDIF(_id, _index) \
-static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
- {.input = &tegra_pll_a_out0, .value = 0}, \
- {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
- {.input = &tegra_pll_p, .value = 2}, \
- {.input = &tegra_clk_m, .value = 3}, \
- { 0, 0}, \
-}
-MUX_I2S_SPDIF(audio0, 0);
-MUX_I2S_SPDIF(audio1, 1);
-MUX_I2S_SPDIF(audio2, 2);
-MUX_I2S_SPDIF(audio3, 3);
-MUX_I2S_SPDIF(audio4, 4);
-MUX_I2S_SPDIF(audio, 5); /* SPDIF */
+ }; \
+ static struct clk tegra_##_name##_2x = { \
+ .name = #_name "_2x", \
+ .ops = &tegra30_clk_double_ops, \
+ .hw = &tegra_##_name##_2x_hw.hw, \
+ .parent_names = _name##_parent_names, \
+ .parents = _name##_parents, \
+ .parent = &tegra_##_name, \
+ .num_parents = 1, \
+ };
+
+AUDIO_SYNC_2X_CLK(audio0, 0);
+AUDIO_SYNC_2X_CLK(audio1, 1);
+AUDIO_SYNC_2X_CLK(audio2, 2);
+AUDIO_SYNC_2X_CLK(audio3, 3);
+AUDIO_SYNC_2X_CLK(audio4, 4);
+AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
+
+static struct clk *tegra_clk_audio_2x_list[] = {
+ &tegra_audio0_2x,
+ &tegra_audio1_2x,
+ &tegra_audio2_2x,
+ &tegra_audio3_2x,
+ &tegra_audio4_2x,
+ &tegra_audio5_2x, /* SPDIF */
+};
+
+#define MUX_I2S_SPDIF(_id) \
+static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
+ "pll_a_out0", \
+ #_id "_2x", \
+ "pll_p", \
+ "clk_m", \
+}; \
+static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
+ &tegra_pll_a_out0, \
+ &tegra_##_id##_2x, \
+ &tegra_pll_p, \
+ &tegra_clk_m, \
+};
+
+MUX_I2S_SPDIF(audio0);
+MUX_I2S_SPDIF(audio1);
+MUX_I2S_SPDIF(audio2);
+MUX_I2S_SPDIF(audio3);
+MUX_I2S_SPDIF(audio4);
+MUX_I2S_SPDIF(audio5); /* SPDIF */
+
+static struct clk tegra_extern1;
+static struct clk tegra_extern2;
+static struct clk tegra_extern3;
/* External clock outputs (through PMC) */
-#define MUX_EXTERN_OUT(_id) \
-static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
- {.input = &tegra_clk_m, .value = 0}, \
- {.input = &tegra_clk_m_div2, .value = 1}, \
- {.input = &tegra_clk_m_div4, .value = 2}, \
- {.input = NULL, .value = 3}, /* placeholder */ \
- { 0, 0}, \
-}
+#define MUX_EXTERN_OUT(_id) \
+static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
+ "clk_m", \
+ "clk_m_div2", \
+ "clk_m_div4", \
+ "extern" #_id, \
+}; \
+static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
+ &tegra_clk_m, \
+ &tegra_clk_m_div2, \
+ &tegra_clk_m_div4, \
+ &tegra_extern##_id, \
+};
+
MUX_EXTERN_OUT(1);
MUX_EXTERN_OUT(2);
MUX_EXTERN_OUT(3);
-static struct clk_mux_sel *mux_extern_out_list[] = {
- mux_clkm_clkm2_clkm4_extern1,
- mux_clkm_clkm2_clkm4_extern2,
- mux_clkm_clkm2_clkm4_extern3,
+#define CLK_OUT_CLK(_name, _index) \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .lookup = { \
+ .dev_id = #_name, \
+ .con_id = "extern" #_index, \
+ }, \
+ .flags = MUX_CLK_OUT, \
+ .fixed_rate = 216000000, \
+ .reg = 0x1a8, \
+ .u.periph = { \
+ .clk_num = (_index - 1) * 8 + 2, \
+ }, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &tegra_clk_out_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
+ .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
+ .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
+ };
+
+CLK_OUT_CLK(clk_out_1, 1);
+CLK_OUT_CLK(clk_out_2, 2);
+CLK_OUT_CLK(clk_out_3, 3);
+
+static struct clk *tegra_clk_out_list[] = {
+ &tegra_clk_out_1,
+ &tegra_clk_out_2,
+ &tegra_clk_out_3,
+};
+
+static const char *mux_sclk[] = {
+ "clk_m",
+ "pll_c_out1",
+ "pll_p_out4",
+ "pll_p_out3",
+ "pll_p_out2",
+ "dummy",
+ "clk_32k",
+ "pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+ &tegra_clk_m,
+ &tegra_pll_c_out1,
+ &tegra_pll_p_out4,
+ &tegra_pll_p_out3,
+ &tegra_pll_p_out2,
+ NULL,
+ &tegra_clk_32k,
+ &tegra_pll_m_out1,
};
-#define CLK_OUT_CLK(_id) \
- { \
- .name = "clk_out_" #_id, \
- .lookup = { \
- .dev_id = "clk_out_" #_id, \
- .con_id = "extern" #_id, \
- }, \
- .ops = &tegra_clk_out_ops, \
- .reg = 0x1a8, \
- .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
- .flags = MUX_CLK_OUT, \
- .max_rate = 216000000, \
- .u.periph = { \
- .clk_num = (_id - 1) * 8 + 2, \
- }, \
- }
-static struct clk tegra_clk_out_list[] = {
- CLK_OUT_CLK(1),
- CLK_OUT_CLK(2),
- CLK_OUT_CLK(3),
+static struct clk tegra_clk_sclk;
+static struct clk_tegra tegra_clk_sclk_hw = {
+ .hw = {
+ .clk = &tegra_clk_sclk,
+ },
+ .reg = 0x28,
+ .max_rate = 334000000,
+ .min_rate = 40000000,
};
-/* called after peripheral external clocks are initialized */
-static void init_clk_out_mux(void)
-{
- int i;
- struct clk *c;
-
- /* output clock con_id is the name of peripheral
- external clock connected to input 3 of the output mux */
- for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
- c = tegra_get_clock_by_name(
- tegra_clk_out_list[i].lookup.con_id);
- if (!c)
- pr_err("%s: could not find clk %s\n", __func__,
- tegra_clk_out_list[i].lookup.con_id);
- mux_extern_out_list[i][3].input = c;
- }
-}
+static struct clk tegra_clk_sclk = {
+ .name = "sclk",
+ .ops = &tegra30_super_ops,
+ .hw = &tegra_clk_sclk_hw.hw,
+ .parent_names = mux_sclk,
+ .parents = mux_sclk_p,
+ .num_parents = ARRAY_SIZE(mux_sclk),
+};
-/* Peripheral muxes */
-static struct clk_mux_sel mux_sclk[] = {
- { .input = &tegra_clk_m, .value = 0},
- { .input = &tegra_pll_c_out1, .value = 1},
- { .input = &tegra_pll_p_out4, .value = 2},
- { .input = &tegra_pll_p_out3, .value = 3},
- { .input = &tegra_pll_p_out2, .value = 4},
- /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
- { .input = &tegra_clk_32k, .value = 6},
- { .input = &tegra_pll_m_out1, .value = 7},
- { 0, 0},
+static const char *mux_blink[] = {
+ "clk_32k",
};
-static struct clk tegra_clk_sclk = {
- .name = "sclk",
- .inputs = mux_sclk,
- .reg = 0x28,
- .ops = &tegra30_super_ops,
- .max_rate = 334000000,
- .min_rate = 40000000,
+static struct clk *mux_blink_p[] = {
+ &tegra_clk_32k,
};
+static struct clk tegra_clk_blink;
+static struct clk_tegra tegra_clk_blink_hw = {
+ .hw = {
+ .clk = &tegra_clk_blink,
+ },
+ .reg = 0x40,
+ .max_rate = 32768,
+};
static struct clk tegra_clk_blink = {
- .name = "blink",
- .parent = &tegra_clk_32k,
- .reg = 0x40,
- .ops = &tegra30_blink_clk_ops,
- .max_rate = 32768,
+ .name = "blink",
+ .ops = &tegra30_blink_clk_ops,
+ .hw = &tegra_clk_blink_hw.hw,
+ .parent = &tegra_clk_32k,
+ .parent_names = mux_blink,
+ .parents = mux_blink_p,
+ .num_parents = ARRAY_SIZE(mux_blink),
};
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
- { .input = &tegra_pll_m, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_pll_a_out0, .value = 3},
- { 0, 0},
+static const char *mux_pllm_pllc_pllp_plla[] = {
+ "pll_m",
+ "pll_c",
+ "pll_p",
+ "pll_a_out0",
};
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
- { .input = &tegra_pll_p, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_m, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
- { 0, 0},
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+ "pll_p",
+ "pll_c",
+ "pll_m",
+ "clk_m",
};
-static struct clk_mux_sel mux_pllp_clkm[] = {
- { .input = &tegra_pll_p, .value = 0},
- { .input = &tegra_clk_m, .value = 3},
- { 0, 0},
+static const char *mux_pllp_clkm[] = {
+ "pll_p",
+ "dummy",
+ "dummy",
+ "clk_m",
};
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_d_out0, .value = 1},
- {.input = &tegra_pll_c, .value = 2},
- {.input = &tegra_clk_m, .value = 3},
- { 0, 0},
+static const char *mux_pllp_plld_pllc_clkm[] = {
+ "pll_p",
+ "pll_d_out0",
+ "pll_c",
+ "clk_m",
};
-static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_m, .value = 1},
- {.input = &tegra_pll_d_out0, .value = 2},
- {.input = &tegra_pll_a_out0, .value = 3},
- {.input = &tegra_pll_c, .value = 4},
- {.input = &tegra_pll_d2_out0, .value = 5},
- {.input = &tegra_clk_m, .value = 6},
- { 0, 0},
+static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+ "pll_p",
+ "pll_m",
+ "pll_d_out0",
+ "pll_a_out0",
+ "pll_c",
+ "pll_d2_out0",
+ "clk_m",
};
-static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
- { .input = &tegra_pll_a_out0, .value = 0},
- /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
- { 0, 0},
+static const char *mux_plla_pllc_pllp_clkm[] = {
+ "pll_a_out0",
+ "dummy",
+ "pll_p",
+ "clk_m"
};
-static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_clk_32k, .value = 2},
- {.input = &tegra_clk_m, .value = 3},
- { 0, 0},
+static const char *mux_pllp_pllc_clk32_clkm[] = {
+ "pll_p",
+ "pll_c",
+ "clk_32k",
+ "clk_m",
};
-static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_clk_m, .value = 2},
- {.input = &tegra_clk_32k, .value = 3},
- { 0, 0},
+static const char *mux_pllp_pllc_clkm_clk32[] = {
+ "pll_p",
+ "pll_c",
+ "clk_m",
+ "clk_32k",
};
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_pll_m, .value = 2},
- { 0, 0},
+static const char *mux_pllp_pllc_pllm[] = {
+ "pll_p",
+ "pll_c",
+ "pll_m",
};
-static struct clk_mux_sel mux_clk_m[] = {
- { .input = &tegra_clk_m, .value = 0},
- { 0, 0},
+static const char *mux_clk_m[] = {
+ "clk_m",
};
-static struct clk_mux_sel mux_pllp_out3[] = {
- { .input = &tegra_pll_p_out3, .value = 0},
- { 0, 0},
+static const char *mux_pllp_out3[] = {
+ "pll_p_out3",
};
-static struct clk_mux_sel mux_plld_out0[] = {
- { .input = &tegra_pll_d_out0, .value = 0},
- { 0, 0},
+static const char *mux_plld_out0[] = {
+ "pll_d_out0",
};
-static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
- { .input = &tegra_pll_d_out0, .value = 0},
- { .input = &tegra_pll_d2_out0, .value = 1},
- { 0, 0},
+static const char *mux_plld_out0_plld2_out0[] = {
+ "pll_d_out0",
+ "pll_d2_out0",
};
-static struct clk_mux_sel mux_clk_32k[] = {
- { .input = &tegra_clk_32k, .value = 0},
- { 0, 0},
+static const char *mux_clk_32k[] = {
+ "clk_32k",
};
-static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
- { .input = &tegra_pll_a_out0, .value = 0},
- { .input = &tegra_clk_32k, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
- { .input = &tegra_pll_e, .value = 4},
- { 0, 0},
+static const char *mux_plla_clk32_pllp_clkm_plle[] = {
+ "pll_a_out0",
+ "clk_32k",
+ "pll_p",
+ "clk_m",
+ "pll_e",
};
-static struct clk_mux_sel mux_cclk_g[] = {
- { .input = &tegra_clk_m, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_clk_32k, .value = 2},
- { .input = &tegra_pll_m, .value = 3},
- { .input = &tegra_pll_p, .value = 4},
- { .input = &tegra_pll_p_out4, .value = 5},
- { .input = &tegra_pll_p_out3, .value = 6},
- { .input = &tegra_pll_x, .value = 8},
- { 0, 0},
+static const char *mux_cclk_g[] = {
+ "clk_m",
+ "pll_c",
+ "clk_32k",
+ "pll_m",
+ "pll_p",
+ "pll_p_out4",
+ "pll_p_out3",
+ "dummy",
+ "pll_x",
};
-static struct clk tegra_clk_cclk_g = {
- .name = "cclk_g",
- .flags = DIV_U71 | DIV_U71_INT,
- .inputs = mux_cclk_g,
- .reg = 0x368,
- .ops = &tegra30_super_ops,
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+ &tegra_pll_m,
+ &tegra_pll_c,
+ &tegra_pll_p,
+ &tegra_pll_a_out0,
+};
+
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_pll_m,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_clkm_p[] = {
+ &tegra_pll_p,
+ NULL,
+ NULL,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_d_out0,
+ &tegra_pll_c,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_m,
+ &tegra_pll_d_out0,
+ &tegra_pll_a_out0,
+ &tegra_pll_c,
+ &tegra_pll_d2_out0,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
+ &tegra_pll_a_out0,
+ NULL,
+ &tegra_pll_p,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_clk_32k,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_clk_m,
+ &tegra_clk_32k,
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_pll_m,
+};
+
+static struct clk *mux_clk_m_p[] = {
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+ &tegra_pll_p_out3,
+};
+
+static struct clk *mux_plld_out0_p[] = {
+ &tegra_pll_d_out0,
+};
+
+static struct clk *mux_plld_out0_plld2_out0_p[] = {
+ &tegra_pll_d_out0,
+ &tegra_pll_d2_out0,
+};
+
+static struct clk *mux_clk_32k_p[] = {
+ &tegra_clk_32k,
+};
+
+static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
+ &tegra_pll_a_out0,
+ &tegra_clk_32k,
+ &tegra_pll_p,
+ &tegra_clk_m,
+ &tegra_pll_e,
+};
+
+static struct clk *mux_cclk_g_p[] = {
+ &tegra_clk_m,
+ &tegra_pll_c,
+ &tegra_clk_32k,
+ &tegra_pll_m,
+ &tegra_pll_p,
+ &tegra_pll_p_out4,
+ &tegra_pll_p_out3,
+ NULL,
+ &tegra_pll_x,
+};
+
+static struct clk tegra_clk_cclk_g;
+static struct clk_tegra tegra_clk_cclk_g_hw = {
+ .hw = {
+ .clk = &tegra_clk_cclk_g,
+ },
+ .flags = DIV_U71 | DIV_U71_INT,
+ .reg = 0x368,
.max_rate = 1700000000,
};
+static struct clk tegra_clk_cclk_g = {
+ .name = "cclk_g",
+ .ops = &tegra30_super_ops,
+ .hw = &tegra_clk_cclk_g_hw.hw,
+ .parent_names = mux_cclk_g,
+ .parents = mux_cclk_g_p,
+ .num_parents = ARRAY_SIZE(mux_cclk_g),
+};
-static struct clk tegra30_clk_twd = {
- .parent = &tegra_clk_cclk_g,
- .name = "twd",
- .ops = &tegra30_twd_ops,
- .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
- .mul = 1,
- .div = 2,
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- .ops = &tegra30_periph_clk_ops, \
- .reg = _reg, \
- .inputs = _inputs, \
- .flags = _flags, \
- .max_rate = _max, \
- .u.periph = { \
- .clk_num = _clk_num, \
- }, \
- }
+static const char *mux_twd[] = {
+ "cclk_g",
+};
-#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
- _flags, _ops) \
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- .ops = _ops, \
- .reg = _reg, \
- .inputs = _inputs, \
- .flags = _flags, \
- .max_rate = _max, \
- .u.periph = { \
- .clk_num = _clk_num, \
- }, \
- }
+static struct clk *mux_twd_p[] = {
+ &tegra_clk_cclk_g,
+};
-#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- .ops = &tegra_clk_shared_bus_ops, \
- .parent = _parent, \
- .u.shared_bus_user = { \
- .client_id = _id, \
- .client_div = _div, \
- .mode = _mode, \
+static struct clk tegra30_clk_twd;
+static struct clk_tegra tegra30_clk_twd_hw = {
+ .hw = {
+ .clk = &tegra30_clk_twd,
+ },
+ .max_rate = 1400000000,
+ .mul = 1,
+ .div = 2,
+};
+
+static struct clk tegra30_clk_twd = {
+ .name = "twd",
+ .ops = &tegra30_twd_ops,
+ .hw = &tegra30_clk_twd_hw.hw,
+ .parent = &tegra_clk_cclk_g,
+ .parent_names = mux_twd,
+ .parents = mux_twd_p,
+ .num_parents = ARRAY_SIZE(mux_twd),
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
+ _max, _inputs, _flags) \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
}, \
- }
-struct clk tegra_list_clks[] = {
- PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
- PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
- PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
- PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
- PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
- PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
- PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
- PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
- PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
- PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
- PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
- PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
- PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
- PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
- PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
- PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
- PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
- PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
- PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
- PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
- PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
-
- PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
- PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
- PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con) \
- { \
- .name = _name, \
- .lookup = { \
+ .lookup = { \
.dev_id = _dev, \
- .con_id = _con, \
+ .con_id = _con, \
}, \
+ .reg = _reg, \
+ .flags = _flags, \
+ .max_rate = _max, \
+ .u.periph = { \
+ .clk_num = _clk_num, \
+ }, \
+ .reset = &tegra30_periph_clk_reset, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &tegra30_periph_clk_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent_names = _inputs, \
+ .parents = _inputs##_p, \
+ .num_parents = ARRAY_SIZE(_inputs), \
+ };
+
+PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
+PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
+PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
+PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
+PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
+PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
+PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
+PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
+PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
+PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
+PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
+PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
+PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
+PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
+PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
+PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
+PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
+PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
+PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
+PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
+
+static struct clk tegra_dsib;
+static struct clk_tegra tegra_dsib_hw = {
+ .hw = {
+ .clk = &tegra_dsib,
+ },
+ .lookup = {
+ .dev_id = "tegradc.1",
+ .con_id = "dsib",
+ },
+ .reg = 0xd0,
+ .flags = MUX | PLLD,
+ .max_rate = 500000000,
+ .u.periph = {
+ .clk_num = 82,
+ },
+ .reset = &tegra30_periph_clk_reset,
+};
+static struct clk tegra_dsib = {
+ .name = "dsib",
+ .ops = &tegra30_dsib_clk_ops,
+ .hw = &tegra_dsib_hw.hw,
+ .parent_names = mux_plld_out0_plld2_out0,
+ .parents = mux_plld_out0_plld2_out0_p,
+ .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
+};
+
+struct clk *tegra_list_clks[] = {
+ &tegra_apbdma,
+ &tegra_rtc,
+ &tegra_kbc,
+ &tegra_timer,
+ &tegra_kfuse,
+ &tegra_fuse,
+ &tegra_fuse_burn,
+ &tegra_apbif,
+ &tegra_i2s0,
+ &tegra_i2s1,
+ &tegra_i2s2,
+ &tegra_i2s3,
+ &tegra_i2s4,
+ &tegra_spdif_out,
+ &tegra_spdif_in,
+ &tegra_pwm,
+ &tegra_d_audio,
+ &tegra_dam0,
+ &tegra_dam1,
+ &tegra_dam2,
+ &tegra_hda,
+ &tegra_hda2codec_2x,
+ &tegra_hda2hdmi,
+ &tegra_sbc1,
+ &tegra_sbc2,
+ &tegra_sbc3,
+ &tegra_sbc4,
+ &tegra_sbc5,
+ &tegra_sbc6,
+ &tegra_sata_oob,
+ &tegra_sata,
+ &tegra_sata_cold,
+ &tegra_ndflash,
+ &tegra_ndspeed,
+ &tegra_vfir,
+ &tegra_sdmmc1,
+ &tegra_sdmmc2,
+ &tegra_sdmmc3,
+ &tegra_sdmmc4,
+ &tegra_vcp,
+ &tegra_bsea,
+ &tegra_bsev,
+ &tegra_vde,
+ &tegra_csite,
+ &tegra_la,
+ &tegra_owr,
+ &tegra_nor,
+ &tegra_mipi,
+ &tegra_i2c1,
+ &tegra_i2c2,
+ &tegra_i2c3,
+ &tegra_i2c4,
+ &tegra_i2c5,
+ &tegra_uarta,
+ &tegra_uartb,
+ &tegra_uartc,
+ &tegra_uartd,
+ &tegra_uarte,
+ &tegra_vi,
+ &tegra_3d,
+ &tegra_3d2,
+ &tegra_2d,
+ &tegra_vi_sensor,
+ &tegra_epp,
+ &tegra_mpe,
+ &tegra_host1x,
+ &tegra_cve,
+ &tegra_tvo,
+ &tegra_dtv,
+ &tegra_hdmi,
+ &tegra_tvdac,
+ &tegra_disp1,
+ &tegra_disp2,
+ &tegra_usbd,
+ &tegra_usb2,
+ &tegra_usb3,
+ &tegra_dsia,
+ &tegra_dsib,
+ &tegra_csi,
+ &tegra_isp,
+ &tegra_csus,
+ &tegra_tsensor,
+ &tegra_actmon,
+ &tegra_extern1,
+ &tegra_extern2,
+ &tegra_extern3,
+ &tegra_i2cslow,
+ &tegra_pcie,
+ &tegra_afi,
+ &tegra_se,
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con) \
+ { \
+ .name = _name, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
}
/* Some clocks may be used by different drivers depending on the board
@@ -1088,23 +1315,24 @@ struct clk *tegra_ptr_clks[] = {
&tegra_pll_x_out0,
&tegra_pll_e,
&tegra_clk_cclk_g,
- &tegra_cml0_clk,
- &tegra_cml1_clk,
- &tegra_pciex_clk,
+ &tegra_cml0,
+ &tegra_cml1,
+ &tegra_pciex,
&tegra_clk_sclk,
&tegra_clk_blink,
&tegra30_clk_twd,
};
-
static void tegra30_init_one_clock(struct clk *c)
{
- clk_init(c);
- INIT_LIST_HEAD(&c->shared_bus_list);
- if (!c->lookup.dev_id && !c->lookup.con_id)
- c->lookup.con_id = c->name;
- c->lookup.clk = c;
- clkdev_add(&c->lookup);
+ struct clk_tegra *clk = to_clk_tegra(c->hw);
+ __clk_init(NULL, c);
+ INIT_LIST_HEAD(&clk->shared_bus_list);
+ if (!clk->lookup.dev_id && !clk->lookup.con_id)
+ clk->lookup.con_id = c->name;
+ clk->lookup.clk = c;
+ clkdev_add(&clk->lookup);
+ tegra_clk_add(c);
}
void __init tegra30_init_clocks(void)
@@ -1116,7 +1344,7 @@ void __init tegra30_init_clocks(void)
tegra30_init_one_clock(tegra_ptr_clks[i]);
for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
- tegra30_init_one_clock(&tegra_list_clks[i]);
+ tegra30_init_one_clock(tegra_list_clks[i]);
for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
@@ -1131,14 +1359,12 @@ void __init tegra30_init_clocks(void)
}
for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
- tegra30_init_one_clock(&tegra_sync_source_list[i]);
+ tegra30_init_one_clock(tegra_sync_source_list[i]);
for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
- tegra30_init_one_clock(&tegra_clk_audio_list[i]);
+ tegra30_init_one_clock(tegra_clk_audio_list[i]);
for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
- tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
+ tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
- init_clk_out_mux();
for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
- tegra30_init_one_clock(&tegra_clk_out_list[i]);
-
+ tegra30_init_one_clock(tegra_clk_out_list[i]);
}
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-08 12:49:05 +0300