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-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Marvell MV88E6xxx DSA switch family
-
-maintainers:
- - Andrew Lunn <andrew@lunn.ch>
-
-description:
- The Marvell MV88E6xxx switch series has been produced and sold
- by Marvell since at least 2008. The switch has a few compatibles which
- just indicate the base address of the switch, then operating systems
- can investigate switch ID registers to find out which actual version
- of the switch it is dealing with.
-
-properties:
- compatible:
- enum:
- - marvell,mv88e6085
- - marvell,mv88e6190
- - marvell,mv88e6250
- description: |
- marvell,mv88e6085: This switch uses base address 0x10.
- This switch and its siblings will be autodetected from
- ID registers found in the switch, so only "marvell,mv88e6085" should be
- specified. This includes the following list of MV88Exxxx switches:
- 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, 6171, 6172, 6175, 6176,
- 6185, 6240, 6320, 6321, 6341, 6350, 6351, 6352
- marvell,mv88e6190: This switch uses base address 0x00.
- This switch and its siblings will be autodetected from
- ID registers found in the switch, so only "marvell,mv88e6190" should be
- specified. This includes the following list of MV88Exxxx switches:
- 6190, 6190X, 6191, 6290, 6361, 6390, 6390X
- marvell,mv88e6250: This switch uses base address 0x08 or 0x18.
- This switch and its siblings will be autodetected from
- ID registers found in the switch, so only "marvell,mv88e6250" should be
- specified. This includes the following list of MV88Exxxx switches:
- 6220, 6250
-
- reg:
- maxItems: 1
-
- eeprom-length:
- $ref: /schemas/types.yaml#/definitions/uint32
- description: Set to the length of an EEPROM connected to the switch. Must be
- set if the switch can not detect the presence and/or size of a connected
- EEPROM, otherwise optional.
-
- reset-gpios:
- description:
- GPIO to be used to reset the whole device
- maxItems: 1
-
- interrupts:
- description: The switch provides an external interrupt line, but it is
- not always used by target systems.
- maxItems: 1
-
- interrupt-controller:
- description: The switch has an internal interrupt controller used by
- the different sub-blocks.
-
- '#interrupt-cells':
- description: The internal interrupt controller only supports triggering
- on active high level interrupts so the second cell must alway be set to
- IRQ_TYPE_LEVEL_HIGH.
- const: 2
-
- mdio:
- $ref: /schemas/net/mdio.yaml#
- unevaluatedProperties: false
- description: Marvell MV88E6xxx switches have an varying combination of
- internal and external MDIO buses, in some cases a combined bus that
- can be used both internally and externally. This node is for the
- primary bus, used internally and sometimes also externally.
-
- mdio-external:
- $ref: /schemas/net/mdio.yaml#
- unevaluatedProperties: false
- description: Marvell MV88E6xxx switches that have a separate external
- MDIO bus use this port to access external components on the MDIO bus.
-
- properties:
- compatible:
- const: marvell,mv88e6xxx-mdio-external
-
- required:
- - compatible
-
-allOf:
- - $ref: dsa.yaml#/$defs/ethernet-ports
-
-required:
- - compatible
- - reg
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethernet-switch@0 {
- compatible = "marvell,mv88e6085";
- reg = <0>;
- reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- sw_phy0: ethernet-phy@0 {
- reg = <0x0>;
- };
-
- sw_phy1: ethernet-phy@1 {
- reg = <0x1>;
- };
-
- sw_phy2: ethernet-phy@2 {
- reg = <0x2>;
- };
-
- sw_phy3: ethernet-phy@3 {
- reg = <0x3>;
- };
- };
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethernet-port@0 {
- reg = <0>;
- label = "lan4";
- phy-handle = <&sw_phy0>;
- phy-mode = "internal";
- };
-
- ethernet-port@1 {
- reg = <1>;
- label = "lan3";
- phy-handle = <&sw_phy1>;
- phy-mode = "internal";
- };
-
- ethernet-port@2 {
- reg = <2>;
- label = "lan2";
- phy-handle = <&sw_phy2>;
- phy-mode = "internal";
- };
-
- ethernet-port@3 {
- reg = <3>;
- label = "lan1";
- phy-handle = <&sw_phy3>;
- phy-mode = "internal";
- };
-
- ethernet-port@5 {
- reg = <5>;
- ethernet = <&fec>;
- phy-mode = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
- };
- - |
- #include <dt-bindings/interrupt-controller/irq.h>
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethernet-switch@0 {
- compatible = "marvell,mv88e6190";
- #interrupt-cells = <2>;
- interrupt-controller;
- interrupt-parent = <&gpio1>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&switch_interrupt_pins>;
- pinctrl-names = "default";
- reg = <0>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch0phy1: ethernet-phy@1 {
- reg = <0x1>;
- };
-
- switch0phy2: ethernet-phy@2 {
- reg = <0x2>;
- };
-
- switch0phy3: ethernet-phy@3 {
- reg = <0x3>;
- };
-
- switch0phy4: ethernet-phy@4 {
- reg = <0x4>;
- };
-
- switch0phy5: ethernet-phy@5 {
- reg = <0x5>;
- };
-
- switch0phy6: ethernet-phy@6 {
- reg = <0x6>;
- };
-
- switch0phy7: ethernet-phy@7 {
- reg = <0x7>;
- };
-
- switch0phy8: ethernet-phy@8 {
- reg = <0x8>;
- };
- };
-
- mdio-external {
- compatible = "marvell,mv88e6xxx-mdio-external";
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy1: ethernet-phy@b {
- reg = <0xb>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-
- phy2: ethernet-phy@c {
- reg = <0xc>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
- };
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethernet-port@0 {
- ethernet = <&eth0>;
- phy-mode = "rgmii";
- reg = <0>;
-
- fixed-link {
- full-duplex;
- pause;
- speed = <1000>;
- };
- };
-
- ethernet-port@1 {
- label = "lan1";
- phy-handle = <&switch0phy1>;
- reg = <1>;
- };
-
- ethernet-port@2 {
- label = "lan2";
- phy-handle = <&switch0phy2>;
- reg = <2>;
- };
-
- ethernet-port@3 {
- label = "lan3";
- phy-handle = <&switch0phy3>;
- reg = <3>;
- };
-
- ethernet-port@4 {
- label = "lan4";
- phy-handle = <&switch0phy4>;
- reg = <4>;
- };
-
- ethernet-port@5 {
- label = "lan5";
- phy-handle = <&switch0phy5>;
- reg = <5>;
- };
-
- ethernet-port@6 {
- label = "lan6";
- phy-handle = <&switch0phy6>;
- reg = <6>;
- };
-
- ethernet-port@7 {
- label = "lan7";
- phy-handle = <&switch0phy7>;
- reg = <7>;
- };
-
- ethernet-port@8 {
- label = "lan8";
- phy-handle = <&switch0phy8>;
- reg = <8>;
- };
-
- ethernet-port@9 {
- /* 88X3310P external phy */
- label = "lan9";
- phy-handle = <&phy1>;
- phy-mode = "xaui";
- reg = <9>;
- };
-
- ethernet-port@a {
- /* 88X3310P external phy */
- label = "lan10";
- phy-handle = <&phy2>;
- phy-mode = "xaui";
- reg = <0xa>;
- };
- };
- };
- };
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-15 11:40:16 +0300