diff options
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 5bd2e8c2f721..bd7628a50b04 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -135,6 +135,7 @@ disable-wp; xlnx,mio-bank = <1>; assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 83757fe0219a..8e66448f35a9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -118,6 +118,7 @@ clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ |