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authorDan Williams <dan.j.williams@intel.com>2022-02-01 04:07:38 +0300
committerDan Williams <dan.j.williams@intel.com>2022-02-09 09:57:29 +0300
commitc978f1b10aba8ce4f8e1f6fcc86b174e08a6e7f7 (patch)
treee2ccbd2808f2653b5eb4e7b8b3577d50c7764d4e /tools/testing/cxl
parenta46cfc0f011ce77d120e1cdbf973f733d18f0105 (diff)
downloadlinux-c978f1b10aba8ce4f8e1f6fcc86b174e08a6e7f7.tar.xz
cxl/port: Up-level cxl_add_dport() locking requirements to the caller
In preparation for moving dport enumeration into the core, require the port device lock to be acquired by the caller. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/164367759016.324231.105551648350470000.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/testing/cxl')
-rw-r--r--tools/testing/cxl/mock_acpi.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/tools/testing/cxl/mock_acpi.c b/tools/testing/cxl/mock_acpi.c
index 4c8a493ace56..c953e3ab6494 100644
--- a/tools/testing/cxl/mock_acpi.c
+++ b/tools/testing/cxl/mock_acpi.c
@@ -57,7 +57,9 @@ static int match_add_root_port(struct pci_dev *pdev, void *data)
/* TODO walk DVSEC to find component register base */
port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
+ cxl_device_lock(&port->dev);
rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE);
+ cxl_device_unlock(&port->dev);
if (rc) {
dev_err(dev, "failed to add dport: %s (%d)\n",
dev_name(&pdev->dev), rc);
@@ -78,7 +80,9 @@ static int mock_add_root_port(struct platform_device *pdev, void *data)
struct device *dev = ctx->dev;
int rc;
+ cxl_device_lock(&port->dev);
rc = cxl_add_dport(port, &pdev->dev, pdev->id, CXL_RESOURCE_NONE);
+ cxl_device_unlock(&port->dev);
if (rc) {
dev_err(dev, "failed to add dport: %s (%d)\n",
dev_name(&pdev->dev), rc);