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| author | Dan Williams <dan.j.williams@intel.com> | 2022-01-24 03:31:56 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-09 09:57:33 +0300 |
| commit | a4a0ce242fcd7022349212c4e2f795762e6ff050 (patch) | |
| tree | 55cf66625ce867dc0ec684ca8f8bc96af20509b7 /tools/testing/cxl | |
| parent | f246abd67ff0dcb471ce2361a913b935d4c8ac11 (diff) | |
| download | linux-a4a0ce242fcd7022349212c4e2f795762e6ff050.tar.xz | |
tools/testing/cxl: Fix root port to host bridge assignment
Mocked root-ports are meant to be round-robin assigned to host-bridges.
Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy")
Link: https://lore.kernel.org/r/164298431629.3018233.14004377108116384485.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/testing/cxl')
| -rw-r--r-- | tools/testing/cxl/test/cxl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index cd2f20f2707f..7e4a0b1ee436 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -558,7 +558,7 @@ static __init int cxl_test_init(void) for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) { struct platform_device *bridge = - cxl_host_bridge[i / NR_CXL_ROOT_PORTS]; + cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)]; struct platform_device *pdev; pdev = platform_device_alloc("cxl_root_port", i); |