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| author | Jani Nikula <jani.nikula@intel.com> | 2023-03-01 18:14:09 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2023-04-11 11:41:57 +0300 |
| commit | 6b8446859c971a5783a2cdc90adf32e64de3bd23 (patch) | |
| tree | 618b63a9d5a1df1e7e75c6cc8d8fab9bb0dd2584 /tools/perf/scripts/python | |
| parent | 09a9639e56c01c7a00d6c0ca63f4c7c41abe075d (diff) | |
| download | linux-6b8446859c971a5783a2cdc90adf32e64de3bd23.tar.xz | |
drm/i915/dsi: fix DSS CTL register offsets for TGL+
On TGL+ the DSS control registers are at different offsets, and there's
one per pipe. Fix the offsets to fix dual link DSI for TGL+.
There would be helpers for this in the DSC code, but just do the quick
fix now for DSI. Long term, we should probably move all the DSS handling
into intel_vdsc.c, so exporting the helpers seems counter-productive.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8232
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230301151409.1581574-1-jani.nikula@intel.com
(cherry picked from commit 1a62dd9895dca78bee28bba3a36f08836fdd143d)
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions