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| author | Arkadi Sharshevsky <arkadis@mellanox.com> | 2017-03-28 18:24:11 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-03-29 03:11:54 +0300 |
| commit | 0f630fcbe5409aaab1a29b48434b28f41bc360ff (patch) | |
| tree | c39071828e549a5a1dc337a55cfd855c1b164c8d /tools/perf/scripts/python | |
| parent | 1555d204e743b6956d2be294a317121f6112238d (diff) | |
| download | linux-0f630fcbe5409aaab1a29b48434b28f41bc360ff.tar.xz | |
mlxsw: reg: Add counter fields to RITR register
Update RITR for counter support. This allows adding counters for
ASIC's router ports.
Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions