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| author | Pierre Gondois <pierre.gondois@arm.com> | 2023-01-04 21:30:24 +0300 |
|---|---|---|
| committer | Sudeep Holla <sudeep.holla@arm.com> | 2023-01-18 00:59:52 +0300 |
| commit | c3719bd9eeb2edf84bd263d662e36ca0ba262a23 (patch) | |
| tree | 2f007a63a19cdeb9ffcc8138be77e991903ae4ce /tools/perf/scripts/python/task-analyzer.py | |
| parent | 1b929c02afd37871d5afb9d498426f83432e71c2 (diff) | |
| download | linux-c3719bd9eeb2edf84bd263d662e36ca0ba262a23.tar.xz | |
cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation
RISC-V's implementation of init_of_cache_level() is following
the Devicetree Specification v0.3 regarding caches, cf.:
- s3.7.3 'Internal (L1) Cache Properties'
- s3.8 'Multi-level and Shared Cache Nodes'
Allow reusing the implementation by moving it.
Also make 'levels', 'leaves' and 'level' unsigned int.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230104183033.755668-2-pierre.gondois@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions