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| author | Hari Nagalla <hnagalla@ti.com> | 2023-05-03 02:15:26 +0300 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2023-06-14 10:35:45 +0300 |
| commit | 257d206b6d117d8e40742dc17ae02406747753ad (patch) | |
| tree | f4c7c27dc9fafc36ff5b1c89711c5c66366b71f8 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 7e5fd896c3d1ecf7b806f5fd42245c1135fe878d (diff) | |
| download | linux-257d206b6d117d8e40742dc17ae02406747753ad.tar.xz | |
arm64: dts: ti: k3-j784s4-main: Add C71x DSP nodes
The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage
domain. The functionality of these DSP subsystems is similar to the C71x
DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of
L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem
has a CMMU but is not currently used. The inter-processor communication
between the main A72 cores and the C71x DSPs is achieved through shared
memory and mailboxes. Add the DT nodes for these DSP processor sub-systems.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Link: https://lore.kernel.org/r/20230502231527.25879-3-hnagalla@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
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