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| author | Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2022-09-09 22:36:18 +0300 |
|---|---|---|
| committer | Damien Le Moal <damien.lemoal@opensource.wdc.com> | 2022-09-16 19:40:23 +0300 |
| commit | 064f14e9df4e7a49940742b8a9af43b48fb4cf00 (patch) | |
| tree | 0438b2605e3ab767036994ef970be5e3bb825033 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 33629d35090f5ce2b1b4ce78aa39954c603536d5 (diff) | |
| download | linux-064f14e9df4e7a49940742b8a9af43b48fb4cf00.tar.xz | |
dt-bindings: ata: ahci: Add Baikal-T1 AHCI SATA controller DT schema
Baikal-T1 AHCI controller is based on the DWC AHCI SATA IP-core v4.10a
with the next specific settings: two SATA ports, cascaded CSR access based
on two clock domains (APB and AXI), selectable source of the reference
clock (though stable work is currently available from the external source
only), two reset lanes for the application and SATA ports domains. Other
than that the device is fully compatible with the generic DWC AHCI SATA
bindings.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions