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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-08-18 12:11:37 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-09-18 09:05:07 +0300 |
| commit | d77fe953768850557a1851d2c933b76b2083e4d5 (patch) | |
| tree | 04fbd504276dfdc9e96cf513efc685d810de1553 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 762dbc444ca240580f7eda5b9152d147cca608b3 (diff) | |
| download | linux-d77fe953768850557a1851d2c933b76b2083e4d5.tar.xz | |
ARM: dts: r8a7793: Convert to new CPG/MSSR bindings
Convert the R-Car M2-N SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions