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| author | Jiri Pirko <jiri@mellanox.com> | 2017-06-06 15:12:04 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-06-06 19:45:23 +0300 |
| commit | be8408e1440cbc86683e4e1c65270ad517b4274a (patch) | |
| tree | c18da9da37f5abda6d8e1d5ef52e21fb6a21a16e /tools/perf/scripts/python/syscall-counts.py | |
| parent | 5a4d1fee2f844813cb2092b7a06b0e20ed9e2fa4 (diff) | |
| download | linux-be8408e1440cbc86683e4e1c65270ad517b4274a.tar.xz | |
mlxsw: pci: Fix size of trap_id field in CQE
The "trap_id" is 9bits long. So far, this was not a problem since we
used only traps with ids that fit into 8bits. But the ACL traps that are
going to be introduced use the 9th bit.
Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation")
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Yotam Gigi <yotamg@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions