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| author | Icenowy Zheng <icenowy@aosc.xyz> | 2016-12-13 18:22:48 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-01-03 00:24:55 +0300 |
| commit | bb021cda2ccf45ee9470bf0f8c55323ad1c761ae (patch) | |
| tree | 215b4d74e53bebc292329acb7046ac9e32a9e686 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 790d929b540661945d1c70652ffb602c5c06ad85 (diff) | |
| download | linux-bb021cda2ccf45ee9470bf0f8c55323ad1c761ae.tar.xz | |
clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33
The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.
Add CLK_SET_RATE_PARENT flag to this clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions