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| author | Wenjing Liu <wenjing.liu@amd.com> | 2023-11-07 00:47:19 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-30 00:48:58 +0300 |
| commit | 613a81995575889753ca44d70d33e84a1d21bae5 (patch) | |
| tree | 715d9d6179c27c452cb4416decfdbfee517230ea /tools/perf/scripts/python/syscall-counts.py | |
| parent | c4290449f8fbecc55013c6125b50908b5359a8fd (diff) | |
| download | linux-613a81995575889753ca44d70d33e84a1d21bae5.tar.xz | |
drm/amd/display: fix a pipe mapping error in dcn32_fpu
[why]
In dcn32 DML pipes are ordered the same as dc pipes but only for used
pipes. For example, if dc pipe 1 and 2 are used, their dml pipe indices
would be 0 and 1 respectively. However
update_pipe_slice_table_with_split_flags doesn't skip indices for free
pipes. This causes us to not reference correct dml pipe output when
building pipe topology.
[how]
Use two variables to iterate dc and dml pipes respectively and only
increment dml pipe index when current dc pipe is not free.
Cc: stable@vger.kernel.org # 6.1+
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions