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| author | Gerhard Engleder <gerhard@engleder-embedded.com> | 2022-09-27 22:58:37 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-09-30 13:31:34 +0300 |
| commit | ff46c610abd62a3dc120dc05ad726b2a47d347ea (patch) | |
| tree | 3601476e89eae72fb67be46741d02dd687e47944 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | d742ea6b8e85f7b0d484bc23392d607b50667da6 (diff) | |
| download | linux-ff46c610abd62a3dc120dc05ad726b2a47d347ea.tar.xz | |
dt-bindings: net: tsnep: Allow dma-coherent
Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.
Add "dma-coherent" property to allow the configuration of cache coherent
DMA.
Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions