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| author | Yanteng Si <siyanteng@loongson.cn> | 2023-06-07 12:21:52 +0300 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2023-06-07 13:42:14 +0300 |
| commit | a4d2b8537845c9a4f4b16dd31793af9c08548341 (patch) | |
| tree | f3539fb9f8c077703aa31d179ddad08ea39b38a8 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 942ccdd834f43b498abc3f022b73fb831d78f5f7 (diff) | |
| download | linux-a4d2b8537845c9a4f4b16dd31793af9c08548341.tar.xz | |
ALSA: hda/intel: Workaround for WALLCLK register for loongson controller
On loongson controller, the value of WALLCLK register
is always 0, which is meaningless, so we return directly.
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Yingkun Meng <mengyingkun@loongson.cn>
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
Link: https://lore.kernel.org/r/185df71ef413ab190460eb377703214ee7288aeb.1686128807.git.siyanteng@loongson.cn
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions