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| author | Imre Deak <imre.deak@intel.com> | 2019-04-19 10:10:26 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2019-04-23 11:05:07 +0300 |
| commit | 9c11b12184bb01d8ba2c48e655509b184f02c769 (patch) | |
| tree | ede0121da0ffd7f223848eb840d4980cc56fe1a9 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 2d6692e642e7ca02883524350038e2a431ef44e8 (diff) | |
| download | linux-9c11b12184bb01d8ba2c48e655509b184f02c769.tar.xz | |
drm/i915/icl: Fix MG_DP_MODE() register programming
Fix the order of lane, port parameters passed to the register macro.
Note that this was already partly fixed by commit
37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters order")
While at it simplify things by using the macro directly instead of an
unnecessary redirection via an array.
v2:
- Add a note the commit message about simplifying things. (José)
Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically consistent")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419071026.32370-1-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions