diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-08-18 12:11:36 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-09-18 09:05:04 +0300 |
| commit | 762dbc444ca240580f7eda5b9152d147cca608b3 (patch) | |
| tree | 1045ceeb34cca020a598ff8bb3fa4768c202d582 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 5802c420636559ffd37095d2886f6964d9b55b11 (diff) | |
| download | linux-762dbc444ca240580f7eda5b9152d147cca608b3.tar.xz | |
ARM: dts: r8a7792: Convert to new CPG/MSSR bindings
Convert the R-Car V2H SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)" and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings
to the new unified "Renesas Clock Pulse Generator / Module Standby and
Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions