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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 19:40:40 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 09:44:49 +0300 |
| commit | 5d6a2165abd4635ecf5ece3d02fe8677f00d32c5 (patch) | |
| tree | 36d048b320c3765fb89913bb53ee00fc0e579311 /tools/perf/scripts/python/stackcollapse.py | |
| parent | d492909c84b895564d7ac413546ae988945c68db (diff) | |
| download | linux-5d6a2165abd4635ecf5ece3d02fe8677f00d32c5.tar.xz | |
ARM: dts: r8a7791: Remove unit-address and reg from integrated cache
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 6f9314ce258c8504 ("ARM: dts: r8a7791: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions