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| author | Atish Patra <atishp@rivosinc.com> | 2023-02-05 04:15:04 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-02-07 18:05:36 +0300 |
| commit | 2723fb7b1e3d331fe6ce04629be6f66898a4cf3b (patch) | |
| tree | b30cf99a38341fd872871b81608fa8d4a7d42c54 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 8929283a687bb4b71ec9d3f1e827aecf829c6b1a (diff) | |
| download | linux-2723fb7b1e3d331fe6ce04629be6f66898a4cf3b.tar.xz | |
RISC-V: Improve SBI PMU extension related definitions
This patch fixes/improve few minor things in SBI PMU extension
definition.
1. Align all the firmware event names.
2. Add macros for bit positions in cache event ID & ops.
The changes were small enough to combine them together instead
of creating 1 liner patches.
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions