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| author | Michal Simek <michal.simek@amd.com> | 2023-05-02 16:35:46 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-05-16 15:50:15 +0300 |
| commit | 116de80adad7a4f1eddff7aa13d801b3c3596eab (patch) | |
| tree | 005dd07297a1b6ca2db036b1b9cdc0804a9c529f /tools/perf/scripts/python/stackcollapse.py | |
| parent | fc57b6c9298f49073fdb6de0532b76b0f98337e4 (diff) | |
| download | linux-116de80adad7a4f1eddff7aa13d801b3c3596eab.tar.xz | |
arm64: zynqmp: Setup clock for DP and DPDMA
Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions