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| author | Jonathan Marek <jonathan@marek.ca> | 2020-04-24 00:09:19 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2020-05-18 19:26:33 +0300 |
| commit | 02ef80c54e7cd70fe1f422b0315fd1534033e382 (patch) | |
| tree | d2631497b77d5e3d0ef6a3e1b0cbf3d17223ee3c /tools/perf/scripts/python/stackcollapse.py | |
| parent | c6ed04f856a4ebbbd8276ea871d8c98590abb0d0 (diff) | |
| download | linux-02ef80c54e7cd70fe1f422b0315fd1534033e382.tar.xz | |
drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650
Update the gmu_pdc registers for A640 and A650.
Some of the RSCC registers on A650 are in a separate region.
Note this also changes the address of these registers:
RSCC_TCS1_DRV0_STATUS
RSCC_TCS2_DRV0_STATUS
RSCC_TCS3_DRV0_STATUS
Based on the values in msm-4.14 and msm-4.19 kernels.
v3: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions