diff options
| author | Steve Wise <swise@opengridcomputing.com> | 2010-09-18 00:40:15 +0400 |
|---|---|---|
| committer | Roland Dreier <rolandd@cisco.com> | 2010-09-28 21:53:50 +0400 |
| commit | 40dbf6ee381008e471d3c4a332971247b7799744 (patch) | |
| tree | 6249fb3fd9cca9e2e42c01a798ef21b4f5a1e328 /tools/perf/scripts/python/netdev-times.py | |
| parent | 410ade4c26bdf256fea3246e968a12409eb08763 (diff) | |
| download | linux-40dbf6ee381008e471d3c4a332971247b7799744.tar.xz | |
RDMA/cxgb4: Fastreg NSMR fixes
- Remove dsgl support - doesn't work in T4.
- Wrap the immediate PBL as needed when building it in the wr.
- Adjust max pbl depth allowed based on ulptx alignment requirements.
- Bump the slots per SQ to 5 to allow up to 128MB fast registers.
- Advertise fastreg support by default.
Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions