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| author | Voon Weifeng <weifeng.voon@intel.com> | 2019-08-27 04:38:11 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-08-28 07:59:38 +0300 |
| commit | 190f73ab4c43ecfc8e93843fe249efeff7d69a90 (patch) | |
| tree | 2fb35df8641af5aad5fdd0a4b276cb05932b136a /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | f6256585fecc9b9d2f0a335a92e864ccae98ea24 (diff) | |
| download | linux-190f73ab4c43ecfc8e93843fe249efeff7d69a90.tar.xz | |
net: stmmac: setup higher frequency clk support for EHL & TGL
EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk,
ptp clock and ptp_max_adj to 200MHz.
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions