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authorMatthew Auld <matthew.auld@intel.com>2024-03-14 19:49:06 +0300
committerMatthew Auld <matthew.auld@intel.com>2024-03-19 12:08:40 +0300
commit2a4172be4013990a794a6ef201c0223b63295423 (patch)
treebc79293befe5a0eaeb363423e77d5a223bf05d82 /tools/perf/scripts/python/failed-syscalls-by-pid.py
parentf87cf2877b16313966a98110888540cdd4c5c051 (diff)
downloadlinux-2a4172be4013990a794a6ef201c0223b63295423.tar.xz
drm/xe/display: mark DPT with XE_BO_PAGETABLE
Otherwise in the case where we use normal system memory, the CPU access will always be cached, like when filling the DPT PTEs, which is likely not what we want since HW access could be incoherent on platforms like LNL. Marking as XE_BO_PAGETABLE will force wc/uc underneath on such platforms. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240314164905.239449-2-matthew.auld@intel.com
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