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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-05-13 00:10:57 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-05-13 22:23:13 +0300 |
| commit | ee0b8e6d02186321be0ea4ec0fb2cbd35bec7e29 (patch) | |
| tree | 102742a5a69a4528c175bd9806271b957a223c14 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 7af4c8451d80d0a8622483c27ab141a7c1a94573 (diff) | |
| download | linux-ee0b8e6d02186321be0ea4ec0fb2cbd35bec7e29.tar.xz | |
dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock
The PRG_ETHERNET registers can add an RX delay in RGMII mode. This
requires an internal re-timing circuit whose input clock is called
"timing adjustment clock". Document this clock input so the clock can be
enabled as needed.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions