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author | Conor Dooley <conor.dooley@microchip.com> | 2023-01-04 21:05:14 +0300 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-02-15 06:24:06 +0300 |
commit | 991994509ee93f7698251e696b8e5591e01b7f68 (patch) | |
tree | 3994f6ba918ba48052854d20b0d9de6af394be4f /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | 7d2078310cbf0fa7fb4323d595fe093c418dcd37 (diff) | |
download | linux-991994509ee93f7698251e696b8e5591e01b7f68.tar.xz |
dt-bindings: riscv: add a capacity-dmips-mhz cpu property
Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
RISC-V has used the generic arch topology code, which provides for
disparate CPU capacities. We never defined a binding to acquire this
information from the DT though, so document the one already used by the
generic arch topology code: "capacity-dmips-mhz".
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230104180513.1379453-3-conor@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions