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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-11-24 22:16:39 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-12-26 13:00:05 +0300 |
| commit | 868695e43b94c7ea08155fee29d57b414b7ab060 (patch) | |
| tree | 63bfca70f810916c85f9aec9232f5fad7d964572 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 1b929c02afd37871d5afb9d498426f83432e71c2 (diff) | |
| download | linux-868695e43b94c7ea08155fee29d57b414b7ab060.tar.xz | |
clk: renesas: r9a09g011: Add PWM clock and reset entries
Add PWM{8..14} clock and reset entries to CPG driver.
The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has
full control of channels 0 to 7, and channel 15, therefore Linux
is only allowed to use channels 8 to 14.
The PWM channel 15 shares apb clock and reset with PWM{8..14}.
The reset is deasserted by the bootloader/ISP.
Add PWM{8..14} clocks to CPG driver and mark apb clock as
critical clock, so that the apb clock will be always on.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221124191643.3193423-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions