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| author | Emil Renner Berthing <kernel@esmil.dk> | 2023-04-01 14:19:13 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-04-05 17:43:15 +0300 |
| commit | 7fce1e39f01900a294cd2c456c77f3e2512e0634 (patch) | |
| tree | 85f891edba674cfb16bf38d621b4bd19e8f1b390 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | eeac8ede17557680855031c6f305ece2378af326 (diff) | |
| download | linux-7fce1e39f01900a294cd2c456c77f3e2512e0634.tar.xz | |
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions