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| author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2019-04-16 11:34:28 +0300 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2019-04-29 16:53:43 +0300 |
| commit | 21c9dfda4b3091535f3e20d036ad5243aeea20f4 (patch) | |
| tree | aecf84bc2bba87d6d2c316b50ed007ff574c4bde /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 02bc723579a8ec84c4a320985e9cae44b087d292 (diff) | |
| download | linux-21c9dfda4b3091535f3e20d036ad5243aeea20f4.tar.xz | |
rtc: imxdi: set range
The RTC Time Counter MSB Register contains the 32 most significant bits
(47:16) of the 47-bit RTC Time Counter. Clocked by a 32.768 KHz clock, this
register is effectively a 32-bit seconds counter.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions