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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-02-14 01:52:57 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-02-21 00:25:30 +0300 |
| commit | 1552dd6ef99fb54479afdd2fb84473b9655cad3c (patch) | |
| tree | abcd189377c49532964838b37358a00de7f4a75f /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 2846cf3fdb8b500e374efdcad3134633dcc5ce60 (diff) | |
| download | linux-1552dd6ef99fb54479afdd2fb84473b9655cad3c.tar.xz | |
drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess
The DSI code has some local hacks to program TRANS_VBLANK on
TGL+ (ICL DSI transcoders didn't have this register). That
will not work when we need to start using the delayed vblank
(for DSB purposes). Too lazy to figure out what the is going
on there, so just sprinkle FIXMEs in the hopes someone else
will spot them eventually.
v2: Only TRANS_{HBLANK,SET_CONTEXT_LATENCY} still no not
exist for DSI transcoders, only TRANS_VBLANK
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-12-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions