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| author | Stephen Boyd <sboyd@kernel.org> | 2023-01-18 21:39:59 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-01-18 21:39:59 +0300 |
| commit | ce45dff1370ea9934d8460eed02507d0c5803b0e (patch) | |
| tree | 1ef019cb46ddecc57af618c973614870d93e1691 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 1b929c02afd37871d5afb9d498426f83432e71c2 (diff) | |
| parent | fbfd614aeaa2853c2c575299dfe2458db8eff67e (diff) | |
| download | linux-ce45dff1370ea9934d8460eed02507d0c5803b0e.tar.xz | |
Merge tag 'renesas-clk-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add PWM, Compare-Match Timer (TIM), USB, SDHI, and eMMC clocks and
resets on RZ/V2M
- Add display clocks on R-Car V4H
- Add Camera Receiving Unit (CRU) clocks and resets on RZ/G2L
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed
clk: renesas: r9a07g044: Add clock and reset entries for CRU
clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
clk: renesas: r9a09g011: Add USB clock and reset entries
clk: renesas: r9a09g011: Add TIM clock and reset entries
clk: renesas: r8a779g0: Add display related clocks
clk: renesas: rcar-gen4: Restore PLL enum sort order
clk: renesas: r8a779g0: Fix OSC predividers
clk: renesas: r9a09g011: Add PWM clock and reset entries
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions