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| author | Paul Hsieh <paul.hsieh@amd.com> | 2018-11-22 13:43:45 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-12-19 02:25:12 +0300 |
| commit | bd4905a9583c760da31ded7256dca6f71483c3dc (patch) | |
| tree | f1dfbfbee5d1fd346cdb51b0965a99174e8c9a6c /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 80adaebd2d411b7d6872a097634848a71eb13d20 (diff) | |
| download | linux-bd4905a9583c760da31ded7256dca6f71483c3dc.tar.xz | |
drm/amd/display: Add retry to read ddc_clock pin
[WHY]
On customer board, there is one pluse (1v , < 1ms) on
DDC_CLK pin when plug / unplug DP cable. Driver will read
it and config DP to HDMI/DVI dongle.
[HOW]
If there is a real dongle, DDC_CLK should be always pull high.
Try to read again to recovery this special case. Retry times = 3.
Need additional 3ms to detect DP passive dongle(3 failures)
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions