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authorJerome Brunet <jbrunet@baylibre.com>2018-01-19 18:55:23 +0300
committerJerome Brunet <jbrunet@baylibre.com>2018-02-12 11:49:23 +0300
commit94aa8a41f1bc807db78567e7031d75998c166150 (patch)
treefb9950ee966d0a46611ab82e8c3769cbb411d8ed /tools/perf/scripts/python/export-to-sqlite.py
parent4ed98e9572ad24a5286d80d71221372b55fa9df5 (diff)
downloadlinux-94aa8a41f1bc807db78567e7031d75998c166150.tar.xz
clk: meson: remove unnecessary rounding in the pll clock
The pll driver performs the rate calculation in Mhz, which adds an unnecessary rounding down to the Mhz of the rate. Use 64bits long integers to perform this calculation safely on meson8b and perform the calculation in Hz instead Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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