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| author | Qiqi Zhang <eddy.zhang@rock-chips.com> | 2022-11-25 13:45:58 +0300 |
|---|---|---|
| committer | Douglas Anderson <dianders@chromium.org> | 2022-11-30 17:40:20 +0300 |
| commit | 8c115864501fc09932cdfec53d9ec1cde82b4a28 (patch) | |
| tree | e6a9002a4105794532bcac4ccfab5f0ecff42c1a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ed14d225cc7c842f6d4d5a3009f71a44f5852d09 (diff) | |
| download | linux-8c115864501fc09932cdfec53d9ec1cde82b4a28.tar.xz | |
drm/bridge: ti-sn65dsi86: Fix output polarity setting bug
According to the description in ti-sn65dsi86's datasheet:
CHA_HSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.
CHA_VSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (Default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.
We should only set these bits when the polarity is negative.
Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver")
Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20221125104558.84616-1-eddy.zhang@rock-chips.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions