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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-08-30 17:52:20 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-09-13 10:47:55 +0300 |
| commit | 83e7d2ec0d7bd57666c6f8fd210255e0ec155c38 (patch) | |
| tree | 107925f69473cc8ff9820564426be5d23998395d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 48e1f50bd67a4ee6c168e5d869cc49096cb2d203 (diff) | |
| download | linux-83e7d2ec0d7bd57666c6f8fd210255e0ec155c38.tar.xz | |
arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions
Use the SoC-specific CPG/MSSR include file to allow future use of
R8A77990_CLK_* symbols.
Replace the hardcoded power domain indices by R8A77990_PD_* symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions