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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2018-12-08 20:12:46 +0300
committerKevin Hilman <khilman@baylibre.com>2019-01-11 03:34:18 +0300
commit7d3f6b536e72c94bd19585a3283e8d141614fee0 (patch)
tree00603dba56dadbce88346994da3ef8f74a1c7d52 /tools/perf/scripts/python/export-to-sqlite.py
parent5938f2c8c8bbdef7cf7746a723f98623a599a0ca (diff)
downloadlinux-7d3f6b536e72c94bd19585a3283e8d141614fee0.tar.xz
ARM: dts: meson8: add the Mali-450 MP6 GPU
Add the Mali-450 GPU and it's OPP table for the Meson8 and Meson8m2 (the latter inherits meson8.dtsi). These SoCs have a Mali-450 GPU with six pixel processors. The OPP table is taken from the 3.10 vendor kernel which uses the following table: FCLK_DEV7 | 1, /* 182.1 Mhz */ FCLK_DEV4 | 1, /* 318.7 Mhz */ FCLK_DEV3 | 1, /* 425 Mhz */ FCLK_DEV5 | 0, /* 510 Mhz */ FCLK_DEV4 | 0, /* 637.5 Mhz */ This describes the mux (FCLK_DEVx) and a 0-based divider in the clock controller. "FCLK" is "fixed_pll" which is running at 2550MHz. The "turbo" setting is described by "turbo_clock = 4" where 4 is the index of the table above. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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