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author | Dan Williams <dan.j.williams@intel.com> | 2022-12-02 00:34:10 +0300 |
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committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-05 21:32:26 +0300 |
commit | 7592d935b7ae71e2b4ff93830743c39a9d13d113 (patch) | |
tree | 03aef29311f2d597adb9c927f9afb50ad1fe307f /tools/perf/scripts/python/export-to-sqlite.py | |
parent | d5b1a27143cb7f78030bb2b6812730992a930c47 (diff) | |
download | linux-7592d935b7ae71e2b4ff93830743c39a9d13d113.tar.xz |
cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem
tl;dr: Clean up an unnecessary export and enable cxl_test.
An RCD (Restricted CXL Device), in contrast to a typical CXL device in
a VH topology, obtains its component registers from the bottom half of
the associated CXL host bridge RCRB (Root Complex Register Block). In
turn this means that cxl_rcrb_to_component() needs to be called from
devm_cxl_add_endpoint().
Presently devm_cxl_add_endpoint() is part of the CXL core, but the only
user is the CXL mem module. Move it from cxl_core to cxl_mem to not only
get rid of an unnecessary export, but to also enable its call out to
cxl_rcrb_to_component(), in a subsequent patch, to be mocked by
cxl_test. Recall that cxl_test can only mock exported symbols, and since
cxl_rcrb_to_component() is itself inside the core, all callers must be
outside of cxl_core to allow cxl_test to mock it.
Reviewed-by: Robert Richter <rrichter@amd.com>
Link: https://lore.kernel.org/r/166993045072.1882361.13944923741276843683.stgit@dwillia2-xfh.jf.intel.com
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions