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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-09-11 20:31:38 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-09-22 00:08:34 +0300 |
| commit | 5b4458ebb4c8007dae7eaeb88cb52b2bb4879894 (patch) | |
| tree | 7fbcf3b8d0c6d5843d39f66b4a39d3d42d67db30 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 501ef013390b774e8e61000a78d1d640d6c3411d (diff) | |
| download | linux-5b4458ebb4c8007dae7eaeb88cb52b2bb4879894.tar.xz | |
ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization
As indicated in the datasheet, a 10ms delay must be observed after
programming the divisors.
The lack of delay prevents the codec to work properly and the playback
appears extremely slow and totally un-audible on a custom sama5 based
board.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20200911173140.29984-2-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions