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| author | Yixun Lan <yixun.lan@amlogic.com> | 2018-01-19 05:09:26 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 11:49:23 +0300 |
| commit | 2fa9b361e500a0e092a9525afbd6a3a363ffa5f0 (patch) | |
| tree | 9cd80ca23d8e175876fb35fedbba445bbb8d8368 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 6b71aceceb09918daf37a40a1221077599040be3 (diff) | |
| download | linux-2fa9b361e500a0e092a9525afbd6a3a363ffa5f0.tar.xz | |
clk: meson: axg: fix the od shift of the sys_pll
According to the datasheet, the od shift of sys_pll is actually 16.
Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[fixed commit message]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions