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| author | Swapnil Jakhade <sjakhade@cadence.com> | 2023-04-03 11:56:44 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-04-12 19:36:26 +0300 |
| commit | 0cfa43ab46b577804a3e89cc5aa7922fe4d9b74f (patch) | |
| tree | c61b432d34809d0895cd35a375a205f135ad49a7 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 45810d486bb44bd60213d5f09a713df81b987972 (diff) | |
| download | linux-0cfa43ab46b577804a3e89cc5aa7922fe4d9b74f.tar.xz | |
phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration
Add register sequences for PCIe + SGMII PHY multilink configuration.
This has been validated on TI J7 platforms.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions