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| author | Dan Williams <dan.j.williams@intel.com> | 2022-01-24 03:31:51 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-09 09:57:33 +0300 |
| commit | f246abd67ff0dcb471ce2361a913b935d4c8ac11 (patch) | |
| tree | 5e6098037f068210a1ca1ac9bfd59111beeaa387 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 9b71e1c9c3aaae5079f5e267785b6f035c5f23da (diff) | |
| download | linux-f246abd67ff0dcb471ce2361a913b935d4c8ac11.tar.xz | |
tools/testing/cxl: Mock dvsec_ranges()
For test purposes, pretend that that CXL DVSEC ranges are not in active
use and the device is ready CXL.mem operation.
Link: https://lore.kernel.org/r/164298431119.3018233.17175518196764977542.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions