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authorAvadhut Naik <avadhut.naik@amd.com>2024-10-22 22:36:29 +0300
committerBorislav Petkov (AMD) <bp@alien8.de>2024-10-31 12:36:07 +0300
commitd4fca1358ea9096f2f6ed942e2cb3a820073dfc1 (patch)
treef4832caf73d7728455cc663fd86ef1186701f564 /tools/perf/scripts/python/export-to-postgresql.py
parente52750fb1458ae9ea5860a08ed7a149185bc5b97 (diff)
downloadlinux-d4fca1358ea9096f2f6ed942e2cb3a820073dfc1.tar.xz
x86/MCE/AMD: Add support for new MCA_SYND{1,2} registers
Starting with Zen4, AMD's Scalable MCA systems incorporate two new registers: MCA_SYND1 and MCA_SYND2. These registers will include supplemental error information in addition to the existing MCA_SYND register. The data within these registers is considered valid if MCA_STATUS[SyndV] is set. Userspace error decoding tools like rasdaemon gather related hardware error information through the tracepoints. Therefore, export these two registers through the mce_record tracepoint so that tools like rasdaemon can parse them and output the supplemental error information like FRU text contained in them. [ bp: Massage. ] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Avadhut Naik <avadhut.naik@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://lore.kernel.org/r/20241022194158.110073-4-avadhut.naik@amd.com
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