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authorMatt Roper <matthew.d.roper@intel.com>2019-09-19 02:56:25 +0300
committerMatt Roper <matthew.d.roper@intel.com>2019-09-19 18:19:41 +0300
commitb01a3ef34816461c31711e5559663e453cb83aba (patch)
treed36d7a105c7a559bafc17ca5d056f34e72b55de8 /tools/perf/scripts/python/export-to-postgresql.py
parenta47e788c2310a59b8e42e0bfc18d810118dff7bf (diff)
downloadlinux-b01a3ef34816461c31711e5559663e453cb83aba.tar.xz
drm/i915: Future-proof DDC pin mapping
We generally assume future platforms will inherit the behavior of the most recent platforms, so update our DDC pin mapping defaults to match how ICP/TGP behave (i.e., pins starting from GMBUS_PIN_1_BXT for combo PHY's and pins starting from GMBUS_PIN_9_TC1_ICP for TC PHY's). MCC's non-standard handling of combo PHY C seems like a platform-specific quirk that is unlikely to be duplicated on future platforms, so continue handling it as a special case. Without this change, future platforms would default to gen4-style pin mapping which is almost certainly not what we'll want. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190918235626.3750-1-matthew.d.roper@intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
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