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| author | Ben Widawsky <ben.widawsky@intel.com> | 2022-02-02 00:28:53 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-09 09:57:30 +0300 |
| commit | 4112a08dd3c5ea0a96029f14061f2320826cfd32 (patch) | |
| tree | d2d8767ebb3d30d153ca69f26eae47802aba399b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 664bf115833c2d4ee717ab63f4e6e72a25c66e77 (diff) | |
| download | linux-4112a08dd3c5ea0a96029f14061f2320826cfd32.tar.xz | |
cxl/pci: Store component register base in cxlds
In preparation for defining a cxl_port object to represent the decoder
resources of a memory expander capture the component register base
address.
The port driver uses the component register base to enumerate the HDM
Decoder Capability structure. Unlike other cxl_port objects the endpoint
port decodes from upstream SPA to downstream DPA rather than upstream
port to downstream port.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[djbw: clarify changelog]
Link: https://lore.kernel.org/r/164375084181.484304.3919737667590006795.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions